Principal Design Verification Engineer , Annapurna Labs
Verify high-speed I/O and scale-up/out components for AWS Inferentia and Trainium systems.
About the role
This role is responsible for verifying high-speed I/O and scale-up/out components across the SoC within Annapurna Labs. The work focuses on hardware solutions for AWS Inferentia and Trainium machine learning data center accelerators.
What you'll do
- Architect and implement end-to-end verification strategies addressing system-wide implications and cross-module interactions.
- Drive unified verification plans across multiple environments, tools, and methodologies.
- Provide technical leadership for verification efforts, guiding architectural decisions and methodology choices.
- Own the technical direction and drive resolution of complex verification challenges at sub-system and chip-level, providing hands-on technical guidance and effective solutions.
- Guide and mentor team members on best practices, methodology improvements, and technical problem-solving.
- Collaborate closely with design, architecture, and software teams to ensure thorough coverage of hardware-software interfaces and cross-module functionality.
What you'll need
- Proven experience leading verification efforts at block, sub-system, or chip level.
- Hands-on experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.
- Experience delivering verification solutions at sub-system and chip level using simulation methodologies.
- Experience verifying high-speed I/O or scale-up/out components across an SoC.
Nice to have
- Experience using multiple verification platforms including formal verification, emulation, and test-generation tools.
Skills: verification strategies, SystemVerilog, formal verification, emulation, SoC verification
More semiconductor jobs: Amazon jobs · Verification engineer jobs · California jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1350
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1350 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1350 |
| Open roles in the wider Digital Design & Verification family | 28 | 3519 · 120 employers |
| Median days open | 28 d | 58 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: verification strategies, SystemVerilog, formal verification, emulation, SoC verification
Who's hiring in this category
- Qualcomm · 118 open roles · median 49 d
- Apple · 114 open roles · median 10 d
- NVIDIA · 105 open roles · median 71 d
- AMD · 87 open roles · median 67 d
- Synopsys · 75 open roles · median 51 d
- SiFive · 57 open roles · median 65 d
How we counted: 1350 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.