Smts Logic Design - Canada

Originally posted 3 August 2026 by the employer.

Develop PCIe Gen6/Gen7 switch IP across architecture definition, micro-architecture, and SystemVerilog RTL implementation through design closure.

About the role

As a Senior Member of Technical Staff (SMTS) – Logic Design Engineer, you will contribute to architecture definition, micro-architecture development, RTL implementation, and design closure of high-performance ASIC IP on the PCIe Switch Architecture and Design team. The role focuses on developing PCIe Gen6/Gen7 switch products.

What you'll do

• Analyze product requirements and contribute to architecture and micro-architecture development for PCIe Gen6/Gen7 switch products.
• Define and document hardware subsystems, including PCIe switch fabric, port controllers, routing and arbitration logic, flow control and credit management, buffer management, power management, and register infrastructure.
• Develop synthesizable RTL using SystemVerilog and design high-performance pipelines supporting PCIe Gen6 and Gen7 data rates.
• Lead significant design blocks, conduct RTL reviews, enforce coding guidelines, and support CDC, RDC, lint, synthesis, and timing closure.
• Collaborate with verification engineers on verification strategies, coverage goals, and debug across block, subsystem, emulation, FPGA, and silicon environments.
• Mentor junior and intermediate engineers, participate in design reviews, and provide technical guidance.

What you'll need

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related discipline.
• 8+ years of ASIC/SoC logic design experience with delivery of complex silicon products from architecture through tape-out.
• Expert knowledge of SystemVerilog, RTL design methodologies, and ASIC development flows.
• Strong understanding of pipelined architectures, resource arbitration, state machine design, clock-domain crossing (CDC), reset-domain crossing (RDC), and low-power design techniques.
• Experience with synthesis and timing closure using EDA tools such as Synopsys Design Compiler/Fusion Compiler, Cadence Genus, SpyGlass, and Questa/Visualizer.

Nice to have

• Knowledge of PCIe Gen5/Gen6/Gen7 protocol architecture and experience designing PCIe switches, root complexes, PCIe endpoints, or high-speed interconnect fabrics.
• Familiarity with CXL, PTM, ATS/PASID/PRI, SR-IOV, and PCIe power management features.
• Experience with emulation platforms such as HAPS, Palladium, or Veloce.
• Experience with performance modeling or architectural simulation in Python or C++.

Skills: RTL implementation, SystemVerilog, PCIe Gen6/Gen7, ASIC logic design, timing closure

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