SIPI Characterization Engineer - Mountain View, CA, United States
$120,000 - $250,000 USD yearly
Originally posted 15 July 2026 by the employer.
About the role
In this role, you will own electrical characterization of high-speed SerDes interfaces and power delivery networks across AI accelerator compute systems. You will build and scale test automation infrastructure covering thousands of channels while collaborating with SIPI engineers and board designers from early concept through production.
What you'll do
- Characterize high-speed SerDes interfaces (PCIe, Ethernet, custom protocols) including BER testing, eye diagram analysis, and PVT characterization. - Perform channel characterization including insertion loss, return loss, and crosstalk measurements using VNA and time-domain reflectometry (TDR). - Measure and analyze high-current power rail transient noise and dynamic voltage droop on complex accelerator power delivery networks. - Characterize PDN impedance from board through package and silicon against target impedance specifications, collaborating to validate mitigation strategies. - Architect, develop, and maintain test automation frameworks for Electrical Design Validation Testing (EDVT) integrating lab instruments (oscilloscopes, BERTs, VNAs, power analyzers) using Python. - Partner with SIPI and board design engineers on advanced package designs (die-to-die interconnects, interposer structures) and PCB stackup, trace routing, and decoupling rules.
What you'll need
- 5–10 years of industry experience in hardware characterization and SI/PI engineering. - Bachelor's degree or higher in Electrical Engineering. - Deep understanding of high-speed SerDes architecture and operation, including PHY layer fundamentals, equalization, jitter decomposition, and link margin analysis. - Strong grasp of transmission line theory, covering wave propagation, impedance matching, reflections, skin effect, and dielectric loss. - Solid understanding of PDN design principles, including target impedance, resonance, bypass capacitor placement, and voltage regulator loop dynamics. - Hands-on proficiency with lab equipment and experience writing test automation scripts in Python.
Nice to have
- Background in AI accelerator or GPU system validation. - Familiarity with JEDEC or PCIe compliance testing methodologies. - Experience with statistical process control (SPC) or large-scale data analysis for silicon characterization. - Ability to do layout review for PCB and advanced package design.
This role has been open 97 days — well below the 112-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
193
|
Median days open
112 d
|
Median salary
$140k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | MatX | All employers we track in this specialty (193 roles · 58 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 193 |
| Open roles in the wider Silicon Validation & Test family | 6 | 2229 · 113 employers |
| Median days open | 97 d | 112 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $140k |
Who's hiring in this category
- Teradyne · 13 open roles · median 120 d
- Renesas Electronics · 12 open roles · median 102 d
- Qualcomm · 11 open roles · median 113 d
- onsemi · 10 open roles · median 135 d
- Infineon Technologies · 9 open roles · median 117 d
- Marvell Technology · 9 open roles · median 117 d
How we counted: 193 open Silicon Test Engineering (Silicon Validation) roles from 58 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.