Silicon Design and Validation Engineer
$120,000 - $192,000 USD yearly
Originally posted 20 April 2026 by the employer — open 143 days.
About the role
This role involves the design, verification, and validation of analog and mixed-signal high-speed building blocks.
What you'll do
- Perform design, verification, and validation of analog and mixed-signal high-speed building blocks.
- Collaborate with cross-functional teams to launch ASIC products for data center networking.
- Conduct bench test debug and validation of clock generation and timing IPs, data converters, TIAs, modulator drivers, clock and data recovery (CDR), and SerDes.
- Assess design bugs and recommend workarounds.
- Develop, debug, and report tests.
What you'll need
- M.Sc. or PhD. in Electrical Engineering or Computer Engineering with 6 years of experience in analog and mixed signal IP design, verification, and validation for high-speed data converters, SerDes, data center networking, and optical I/O.
- Experience with design, validation, and verification of analog front-end circuits, Trans-Impedance Amplifiers (TIA), PLLs, VCOs, and clocking circuitry.
- Knowledge of development methodologies, design flows including EDA integration, foundry PDK, and associated collaterals.
- Experience with validation, verification, and characterization of control loops such as PLLs and LDOs.
- Deep understanding of signal integrity and power integrity for high-speed designs and experience with PI and SI measurements for correlation and debugging purposes.
- Ability to work with Matlab or Python.
- Experience with measurement equipment such as DCO, oversampling/real time scopes, and network analyzers.
- System-level knowledge and deep understanding of current generation and optical and electrical high-speed I/Os.
- Understanding of high-speed optical and electrical interconnect architectures and IEEE standards.
Nice to have
- Experience with RF and high speed probing.
- Understanding of advanced packaging (2.5D / 3D) architectures.
Skills: analog and mixed-signal, high-speed building blocks, data converters, SerDes, optical I/O, CDRs
This role has been open 142 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 11 | 217 |
| Median days open | 142 d | 91 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: analog and mixed-signal, high-speed building blocks, data converters, SerDes, optical I/O, CDRs
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom (this employer) · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.