Signal/Power Integrity Engineer (On-/Off-Chip) - Seoul HQ, South Korea
Originally posted 6 August 2026 by the employer — open 35 days.
About the role
This role involves defining SI/PI requirements, performing simulations, and developing methodologies for advanced packaging technologies. The scope covers SI/PI analysis and optimization across on-chip, package, and PCB domains, including chiplet and 3D-IC interfaces.
What you'll do
- Define SI/PI requirements based on IP and system-level specifications.
- Perform SI/PI simulations at electromagnetic (EM), circuit, and system levels.
- Develop SI/PI methodologies for advanced packaging technologies (chiplet, 3D-IC, D2D, C2C).
- Provide design guidance on stack-up, interconnect routing, PDN architecture, and decoupling strategy.
- Collaborate with silicon, package, and board teams to ensure measurement-simulation correlation.
- Support debug and bring-up efforts in the lab.
What you'll need
- BS or MS in Electrical Engineering, Physics, or a related field.
- 8+ years of experience in component- and system-level SI/PI analysis.
- Solid understanding of SI/PI fundamentals and methodologies.
- Hands-on experience with VNA, TDR, and real-time oscilloscopes.
- Proficient in EDA tools such as SIwave, HFSS, ADS, HSPICE, Allegro, RedHwak-SC, SC-ET, or RedHawk-3DIC.
Nice to have
- PhD in Electrical Engineering, Physics, or a related field with 5+ years of relevant industry experience.
- SI/PI analysis and optimization for high-speed digital systems and standard interfaces (PCIe, DDR, Ethernet).
- Experience modeling and analyzing complex 3D structures using EM simulation tools.
- Experience with on-chip Backend sign-off (Static/Dynamic IR, EM).
- Experience with on-/off-chip PDN modeling and budgeting.
- Experience with on-chip glitch/jitter/DVD analysis and sign-off methodology, including cross-talk, TSV uncertainty, and multi-corner/process derating.
- Experience with early-stage reference clock jitter estimation and sign-off methodology development.
- Experience with on-chip clock sign-off, including clock design guide, 3DIC jitter derating, and multi-corner/process variation analysis.
Skills: SI/PI simulations, advanced packaging, chiplet, 3D-IC, PCIe, DDR, Ethernet
This role has been open 35 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | FuriosaAI | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1317 · 100 employers |
| Median days open | 35 d | 91 d (−56 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI/PI simulations, advanced packaging, chiplet, 3D-IC, PCIe, DDR
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.