Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging - Austin, Texas, United States
Originally posted 8 September 2026 by the employer — open 13 days.
About the role
This role involves Signal or Power Integrity (SI/PI) analysis and optimization of advanced packaging solutions for machine learning and data center ASICs.
What you'll do
- Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures.
- Support package stack-up design, including dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies.
- Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) or analyze package PDN performance (decoupling effectiveness, plane resonance, IR drop, AC impedance).
- Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for signal or power paths.
- Build and validate models for decoupling technologies such as on-die capacitance, deep trench capacitors (DTCs), or IPD capacitors.
- Coordinate with SoC die-level teams and board design teams to gather requirements and support co-optimization of package architecture.
What you'll need
- Experience with package-level SI or PI simulations.
- Experience with 2.5D, 3D-IC, fan-out, or silicon interposer/bridge architectures.
- Knowledge of high-speed channel simulations.
- Understanding of PDN performance analysis.
- Experience modeling advanced interconnects.
- Experience building and validating models for decoupling technologies.
- Ability to coordinate with SoC die-level teams and board design teams.
Skills: package-level SI/PI, 2.5D/3D-IC, silicon interposer, high-speed channel simulations, PDN performance, advanced interconnects
This role has been open 12 days — well below the 38-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
67
|
Median days open
38 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (67 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 67 |
| Median days open | 26 d | 38 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: package-level SI/PI, 2.5D/3D-IC, silicon interposer, high-speed channel simulations, PDN performance, advanced interconnects
Who's hiring in this category
- Micron Technology · 13 open roles · median 143 d
- AMD · 6 open roles · median 27 d
- Marvell Technology · 6 open roles · median 13 d
- Broadcom · 5 open roles · median 163 d
- NVIDIA · 5 open roles · median 38 d
- Amazon (this employer) · 4 open roles · median 26 d
How we counted: 67 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 24 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.