Signal Integrity SI PI Engineer - Jhubei City, Taiwan
Analog & Mixed-Signal Design
Originally posted 24 July 2026 by the employer — open 48 days.
This role focuses on improving SI/PI performance for probe cards.
About the role
This role is responsible for completing tasks and solving short and long term problems within the Signal Integrity group.
What you'll do
- Perform signal and power integrity analysis for high-speed interconnects (PCB, package, MLO, probe card).
- Develop and validate electrical models for transmission lines, vias, connectors, and PDN structures.
- Use EM and circuit tools (HFSS, ADS, SIwave, PowerSI) for frequency-domain and time-domain analysis.
- Build system/channel models (IBIS-AMI, eye diagrams) and run what-if studies.
- Drive simulation-to-measurement correlation and root cause analysis.
- Define SI validation plans using VNA, TDR, TDT and high-speed measurement setups.
What you'll need
- BS/MS in Electrical Engineering or related field.
- 4+ years of relevant experience in SI/PI analysis and design.
- Strong understanding of transmission line theory, power integrity principles, crosstalk, and signal degradation mechanisms.
- Experience with tools such as HFSS, ADS, SIwave, PowerSI, PowerDC, SPICE, Allegro, MATLAB.
Nice to have
- Hands-on experience with measurement tools (VNA, TDR/TDT).
- Experience with high-speed interfaces (PAM4, SerDes, PCIe, HBM).
- Scripting/automation (Python, MATLAB).
- Experience in advanced packaging, probe cards, or fine-pitch interconnects.
Market context
This role has been open 48 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | FormFactor | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 89 d | 91 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.