Signal Integrity & Power Integrity Principal Engineer - San Jose, California, United States
$187,000 - $270,000 USD yearly
Originally posted 16 May 2026 by the employer — open 117 days.
About the role
This role involves leading the design, verification, and optimization of high-speed interconnects across silicon, IC package, and board-level architectures.
What you'll do
- Lead end-to-end signal and power integrity design for IC packages, validation platforms, and development kit hardware.
- Define and deploy SI/PI simulation methodologies leveraging advanced EDA tools.
- Perform detailed simulation, review, and trade-off analysis of package and board designs.
- Diagnose and resolve complex system-level SI/PI challenges.
- Collaborate across silicon, package, and board design teams to define optimized electrical solutions.
- Drive forward-looking SI/PI technologies, including advanced and heterogeneous packaging solutions.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of hands-on experience in Signal Integrity and Power Integrity engineering across silicon, package, and board-level designs.
- Deep expertise in high-speed digital interfaces, SI/PI fundamentals, and power delivery network behavior.
- Proficiency with industry-standard simulation and modeling tools such as ANSYS HFSS, Synopsys HSPICE, Cadence Sigrity, Keysight ADS, or equivalent platforms.
- Strong analytical skills to interpret, correlate, and validate simulation, design, and measurement data.
- Hands-on experience with silicon/package/board layout and design tools (e.g., Mentor Graphics, Cadence Allegro).
Nice to have
- Scripting and automation experience using Python, MATLAB, or similar languages.
- Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
Skills: Signal Integrity, Power Integrity, high-speed interconnects, IC package, board-level architectures, ANSYS HFSS
This role has been open 115 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 5 | 217 |
| Median days open | 57 d | 91 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signal Integrity, Power Integrity, high-speed interconnects, IC package, board-level architectures, ANSYS HFSS
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.