Signal Integrity Engineer - Richardson, Texas, United States of America, United States
$153,000 - $296,000 USD yearly
Originally posted 31 July 2026 by the employer.
Lead SI/PI strategy, die-package-board co-design, and electrical signoff for custom silicon products developed by MIPS.
About the role
This role leads signal integrity and power integrity strategy, die-package-board co-design, and electrical performance optimization across silicon, package, and board domains. The focus covers custom silicon products developed by MIPS across industrial, automotive, AI, and networking applications.
What you'll do
- Define electrical architecture, package power delivery networks, high-speed interfaces, board topologies, and channel implementations. - Drive die-package-board co-design, including IO planning, bump assignment, floorplan optimization, package routing, board stackup definition, and power delivery network design. - Perform and direct signal integrity (SI), power integrity (PI), electromagnetic (EM), and channel compliance simulations across die, package, and board environments. - Establish SI/PI signoff methodologies, design guidelines, and design closure criteria across multiple engineering disciplines. - Define validation strategies, characterization requirements, compliance testing, simulation-to-silicon correlation, and electrical root-cause analysis during silicon bring-up. - Drive technical alignment and execution with customers, package vendors, PCB vendors, OSAT partners, and ecosystem suppliers.
What you'll need
- Master's degree or higher in Electrical Engineering, Computer Engineering, Applied Physics, Electromagnetics, or a related field. - Minimum 10+ years of semiconductor experience in Signal Integrity, Power Integrity, Electrical Design, Package Design, System Design, or Die-Package-Board Co-Design. - Minimum 5+ years of experience leading SI/PI activities for complex SoCs, ASICs, high-speed interfaces, high-performance computing platforms, or heterogeneous systems. - Working knowledge of high-speed electrical interfaces including PCIe, Ethernet, DDR/LPDDR, SerDes, UCIe, USB, and MIPI. - Working knowledge of EDA simulation tools such as Cadence Sigrity, Cadence Clarity, Ansys HFSS, SIwave, and Q3D. - Experience with packaging technologies including Flip-Chip, FCBGA, WLCSP, wire-bond, interposers, chiplets, 2.5D, and 3D integration.
Nice to have
- Experience in ASIC or SoC development covering high-speed interfaces, networking, AI/ML, datacenter, automotive, mixed-signal, or HPC products. - Experience engaging with package vendors, PCB vendors, OSAT partners, and foundries across advanced packaging roadmaps. - Experience with advanced packaging technologies including chiplets, UCIe, HBM-based systems, 2.5D/3D integration, and heterogeneous integration architectures. - Experience developing and deploying enterprise-wide SI/PI methodologies, electrical signoff flows, and best practices across multiple product teams. - Contributions to industry standards, technical conferences, patents, or publications in signal integrity, power integrity, or advanced packaging.
Skills: die-package co-design, package architecture, signal integrity, power integrity, thermal analysis, DFM/DFT
This role has been open 222 days — well above the 58-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
214
|
Median days open
58 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (214 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 214 |
| Open roles in the wider Process, Fab & Equipment family | 405 | 10096 · 107 employers |
| Median days open | 222 d | 58 d (+164 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: die-package co-design, package architecture, signal integrity, power integrity, thermal analysis, DFM/DFT
Who's hiring in this category
- Renesas Electronics · 30 open roles · median 39 d
- Infineon Technologies · 25 open roles · median 43 d
- Micron Technology · 21 open roles · median 42 d
- onsemi · 17 open roles · median 32 d
- Intel Corporation · 11 open roles · median 111 d
- Monolithic Power Systems · 11 open roles · median 221 d
How we counted: 214 open Packaging Engineering (Packaging) roles from 41 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.