Signal Integrity Engineer – Memory Interface
Prior design and modeling experience with DDR or LPDDR interfaces is required for this package-to-board memory interface role.
About the role
This role is responsible for memory interface signal integrity for mobile device SoCs, spanning package to board. The scope centers on design and modeling for DDR or LPDDR interfaces.
What you'll do
- Work on electrical and physical design of memory systems.
- Perform electrical extraction and validation of package and MLB.
- Collaborate with circuit and controller teams to optimize memory system design.
- Conduct SI and PI modeling, simulation, and characterization of memory interfaces.
- Develop and execute test plans to validate signal and power integrity.
- Work with product engineering and system engineering to debug and improve product yield.
What you'll need
- BS degree with 10+ years of industry experience.
- Prior design and modeling experience with DDR or LPDDR interfaces.
- Familiarity with signal and power integrity issues of memory interfaces.
- Experience with product package/board design and analysis, PI/SI methodology development, and lab correlation/validation of simulation results.
- Experience with lab equipment including VNA, TDR, real-time scope, and spectrum analyzer.
- Working knowledge of 3D/2D EM simulation tools and transmission line theory.
- Proficiency in Python with foundational coding skills.
Nice to have
- MSEE with 8+ years of industry experience, or a Ph.D.
- Expertise in leveraging generative AI coding assistants to enhance productivity.
Skills: signal integrity, power integrity, memory interface, EM simulation, VNA
More semiconductor jobs: Apple San Diego jobs · Signal integrity jobs
This role has been open 0 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
255
|
Median days open
76 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (255 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 255 |
| Open roles in the wider Analog & Mixed-Signal family | 79 | 1538 · 114 employers |
| Median days open | 0 d | 76 d (−76 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: signal integrity, power integrity, memory interface, EM simulation, VNA
Who's hiring in this category
- Synopsys · 35 open roles · median 38 d
- AMD · 24 open roles · median 46 d
- Cadence Design Systems · 21 open roles · median 150 d
- Qualcomm · 17 open roles · median 84 d
- NVIDIA · 16 open roles · median 211 d
- Micron Technology · 11 open roles · median 49 d
How we counted: 255 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 51 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.