Signal Integrity Engineer - USA-CA San Jose Innovation Drive, United States
$141,300 - $226,000 USD yearly
Originally posted 13 July 2026 by the employer — open 59 days.
About the role
This role is for an experienced Signal Integrity Engineer focusing on parallel interfaces, contributing to both customer products and the development of new interconnect technologies and IP in the MCM, 2.5D, and 3D spaces.
What you'll do
- Perform mask-based timing signoff using time domain simulations (SPICE, etc.) of parallel interfaces including 2.5D and 3D.
- Conduct electromagnetic extraction and modeling of signal and power delivery channels (PCB, Package, Interposers, etc.).
- Analyze AC and transient characteristics of Power Distribution Networks.
- Perform IO channel analysis.
- Create pre-layout models of transceivers, signal, and PDN networks.
- Automate sign-off processes and collaborate with EDA suppliers to enhance tool accuracy and analysis flow.
- Generate analysis results, presentations, and sign-off reports, supporting pre-sales activities.
What you'll need
- Knowledge of at least one DDR/LPDDR and/or HBM SI/PI sign-off flow tool suite.
- Experience with various IC, Package, and PCB database types.
- TCL, Python scripting experience for automating routine tasks.
- Bachelor in Electrical/Electronics/Computer Engineering and 8+ years related experience OR Masters Degree in Electrical/Electronics/Computer Engineering and 6+ years related experience.
Skills: SI/PI, DDR/LPDDR, HBM, 2.5D/3D, SPICE
This role has been open 164 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 11 | 217 |
| Median days open | 142 d | 91 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI/PI, DDR/LPDDR, HBM, 2.5D/3D, SPICE
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom (this employer) · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.