Signal Integrity Engineer - Livermore, CA, United States
$134,056 - $166,100 USD yearly
Originally posted 25 June 2026 by the employer — open 77 days.
About the role
This role involves improving Signal Integrity and Power Integrity (SI/PI) performances and conducting production design analysis. The position focuses on probe card development within the Design Group.
What you'll do
- Improve Signal Integrity and Power Integrity (SI/PI) performances.
- Measure, characterize, and complete production design analysis.
- Perform lab measurements and correlate to simulations to refine future models.
- Model and design power distribution and high-density input and outputs (I/O) on Printed Circuit Boards (PCB), packages, connectors, and probe cards.
- Provide, document, and train the Design Organization on design constraints, specifications, and solutions for PCB and package layout based on Signal Integrity.
- Support probe card development by improving understanding of Signal Integrity fundamentals.
What you'll need
- Master’s degree or foreign equivalent in Electrical Engineering or related field.
- 2 years of experience as Signal Integrity Engineer or related occupation.
- 1 year of prior work experience in transmission line theory, impedance control, and stack-up design.
- 1 year of prior work experience in analyzing board files using Cadence Allegro to ensure optimal SI/PI performance.
- 1 year of prior work experience in measuring s-parameters of PCBs using Vector Network Analyzer.
- 1 year of prior work experience in characterizing performance of a trace in a PCB using a Time Domain Reflectometer.
- 1 year of prior work experience in performing and proper handling of RF measurement micro probes to measure PCBs.
- 1 year of prior work experience in analyzing s-parameters and TDR data to characterize PCBs.
- 1 year of prior work experience in layout guidelines for minimizing crosstalk, reflections, and EMI.
Skills: signal integrity, transmission line theory, impedance control, s-parameters, TDR
This role has been open 77 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | FormFactor | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 89 d | 91 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: signal integrity, transmission line theory, impedance control, s-parameters, TDR
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.