Signal Integrity Architect - Santa Clara, California, United States of America
$220,200 - $330,400 USD yearly
Originally posted 8 May 2026 by the employer — open 125 days.
This role focuses on high-performance signal integrity (SI) solutions for server applications based on Qualcomm's Snapdragon SoC.
About the role
This individual contributor Signal Integrity Architect will develop high-performance signal integrity (SI) solutions tailored for advanced server applications. You will lead the definition, analysis, and verification of SI for high-speed interconnects across die, interposer, package, PCB, and system levels for data center servers.
What you'll do
- Collaborate with SoC, applications engineering, packaging, and system design teams to define and implement system interconnects.
- Provide guidelines and feedback on silicon timing, bump/RDL, package pinout and PCB specifications.
- Develop customer guidelines and define module interfaces/formats for simulation.
- Lead the creation of server-grade SI models, simulations, and final designs.
- Perform early SI analysis on 2.5D/3D structures and establish design guidelines.
- Update and automate design and analysis flows.
- Prepare and present technical documentation and reports to stakeholders.
What you'll need
- Master’s degree in Electrical or Computer Engineering, with a specialization in Signal Integrity (SI).
- 6 years of experience in SI analysis, simulation, and measurement of high-speed digital systems.
- Strong knowledge of SI fundamentals, including power distribution networks (PDN), EMIR, transmission line theory, crosstalk, S-parameters, and channel simulations.
- Expertise in DDR5/LPDDR5X JEDEC specifications and/or SerDes standards (PCIe, CXL, USB, Ethernet).
- Experience in developing SI methodologies from die to system, with lab correlation and validation.
- Proficiency with 2D/2.5D/3D EM simulation tools such as ANSYS HFSS, Cadence Sigrity, Dassault Systèmes CST, Keysight ADS, and Synopsys' HSPICE.
- Hands-on experience creating complex SI models and performing both frequency and time-domain simulations.
- Proficiency in Unix/Linux environments and experience with EDA tools through scripting.
- Strong knowledge of packaging and PCB technologies, design, and manufacturing processes.
- Familiarity with 2.5D/3D packaging technologies, such as CoWoS, InFo, EMIB, and RDL.
- Hands-on experience with electrical validation and compliance testing using tools like VNAs, oscilloscopes, spectrum analyzers, PCIe/I2C analyzers, traffic generators, TDR, and differential probes.
Nice to have
- Ph.D. in Electrical or Computer Engineering, specializing in SI.
- 10 years of experience in SI analysis, simulation, and measurement of high-speed digital systems.
- In-depth understanding of computational electromagnetics and transmission line theory.
- Proficiency in DDR5 and LPDDR5X timing budgets, jitter analysis, and PHY design/link analysis.
- Experience with SI simulation for PCIe Gen6, multi-gigabit serial buses (112Gbps), UCIE.
- Experience with package and PCB design tools such as Cadence Allegro.
- Proficiency in scripting with MATLAB, Perl, and Python.
Skills: Signal Integrity (SI), DDR5/LPDDR5X JEDEC, SerDes standards (PCIe, CXL, USB, Ethernet), 2.5D/3D EM simulation tools, ANSYS HFSS, Cadence Sigrity, CST, Keysight ADS, HSPICE, 2.5D/3D packaging technologies
This role has been open 154 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 17 | 217 |
| Median days open | 74 d | 91 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signal Integrity (SI), DDR5/LPDDR5X JEDEC, SerDes standards (PCIe, CXL, USB, Ethernet), 2.5D/3D EM simulation tools, ANSYS HFSS, Cadence Sigrity, CST, Keysight ADS, HSPICE, 2.5D/3D packaging technologies
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm (this employer) · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.