Signal and Power Integrity Engineer - SIO Interface - San Francisco Bay Area, United States
Originally posted 25 August 2026 by the employer.
This role focuses on signal integrity and power integrity for Apple SOCs, covering silicon to package to board.
About the role
This role involves high-speed serial interface signal integrity and power integrity for Apple SOCs, spanning from silicon to package to board. You will be part of the team developing SOCs used within Apple devices.
What you'll do
- Work on the electrical and physical design of high-speed serial interface systems.
- Perform electrical extraction and validation of package and PCB.
- Optimize circuit and system design SI and PI modeling, simulation, and characterization of high-speed serial interface.
- Develop and execute test plans to validate signal and power integrity.
- Debug and improve product yield with product engineering and system engineering.
What you'll need
- Bachelor's degree.
- Familiarity with signal integrity and power integrity issues of high speed serial interfaces.
- Experience with actual product package/board design and analysis.
- Experience with SI/PI methodology development.
- Experience with lab correlation/validation of simulation results.
- Strong fundamentals in 3D/2D EM simulation tools and transmission line theory.
Nice to have
- PhD in a relevant field.
- BS and 5+ years or MS and 3+ years of relevant industry experience.
- Prior design and modeling experience with USB, PCIe, or comparable interfaces.
- Familiarity with lab equipment, such as VNA, TDR, real-time scope, spectrum analyzer.
Skills: signal integrity, power integrity, high speed serial interfaces, EM simulation, VNA, TDR
This role has been open 34 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 39 | 1385 · 107 employers |
| Median days open | 7 d | 76 d (−69 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: signal integrity, power integrity, high speed serial interfaces, EM simulation, VNA, TDR
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple (this employer) · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.