Signal and Power Integrity Engineer
Analog & Mixed-Signal Design
About the role
This role involves designing, simulating, and validating signal and power delivery networks for high-speed digital systems, including PCBs, packages, and interconnects.
What you'll do
- Design, simulate, and validate signal and power delivery networks for high-speed digital systems.
- Analyze and optimize signal and power integrity performance using simulation tools.
- Develop and maintain signal and power integrity design guidelines and best practices.
- Collaborate with product engineering and manufacturing teams to ensure signal and power integrity requirements are met.
- Develop and maintain test plans and procedures for signal and power integrity testing.
- Troubleshoot signal and power integrity issues and implement design changes.
What you'll need
- Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or related field.
- Minimum 5 years of experience in signal and power integrity engineering.
- Strong knowledge of signal and power integrity principles, including transmission line theory, electromagnetic compatibility, and power delivery network design.
- Proficiency in lab measurement with simulation tools such as ANSYS, Cadence, or CST.
- Experience with design for manufacturability (DFM) and design for test ability (DFT) principles.
- Strong analytical and problem-solving skills to troubleshoot complex signal and power integrity issues.
Skills: signal integrity, power integrity, high-speed digital systems, simulation tools, ANSYS, Cadence
Market context
This role has been open 128 days — well above the 89-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
215
|
Median days open
89 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | Market (215 open roles · 44 companies) |
|---|---|---|
| Open roles in category | 5 | 215 |
| Median days open | 75 d | 89 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: signal integrity, power integrity, high-speed digital systems, simulation tools, ANSYS, Cadence
Who's hiring in this category
- AMD · 24 open roles · median 60 d
- Cadence Design Systems · 19 open roles · median 152 d
- Qualcomm · 18 open roles · median 68 d
- Synopsys · 16 open roles · median 52 d
- Broadcom · 11 open roles · median 141 d
- Micron Technology · 9 open roles · median 126 d
Based on 215 open roles at 44 companies in our index. Snapshot 9 Sept 2026.