SI/PI Engineer - San Jose, United States
Originally posted 30 April 2026 by the employer.
About the role
As a Signal Integrity and Power Integrity (SI/PI) Engineer on the platform electrical engineering team, you will own the SI/PI methodology for high-speed PCB and system designs from architecture through final release. The role focuses on ensuring electrical margins across high-speed serial interfaces including PCIe Gen5/Gen6 and 112G/224G Ethernet.
What you'll do
- Perform pre- and post-layout SI simulations for high-speed serial interfaces, including PCIe Gen5/Gen6 and 112G/224G Ethernet. - Conduct channel analysis and link budget calculations while defining topology constraints, trace geometry, stack-up requirements, and via optimization guidelines. - Develop and maintain COM, IBIS, S-parameter, and SPICE models, correlating simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis, including target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance using Cadence Allegro / Sigrity or Ansys SIwave. - Support bring-up, debug signal quality issues, and maintain simulation-to-hardware correlation databases.
What you'll need
- B.S. or M.S. in Electrical Engineering or a closely related discipline. - 5+ years of hands-on SI/PI experience on high-speed designs (>1 Gbps serial links or DDR4/5 and HBM3/4 memory interfaces). - Proficiency with industry SI/PI EDA tools, such as Cadence Sigrity, Ansys SIwave/HFSS, Keysight ADS, or equivalent. - Strong understanding of transmission line theory, return-loss, insertion-loss, crosstalk, eye-diagram analysis, and jitter decomposition. - Experience with PDN modelling, target impedance methodology, and DC IR analysis. - Working knowledge of multi-layer PCB stack-up design and controlled-impedance trace routing. - Hands-on lab skills in S-parameter measurements with VNA, time-domain reflectometry (TDR), BERT operation, and oscilloscope probing techniques.
Nice to have
- Prior work in data center, AI/ML accelerator, networking, or high-performance computing (HPC) hardware environments. - Experience scripting automated SI/PI simulation flows using Python or MATLAB.
Skills: SI simulations, high-speed serial interfaces, PCIe Gen5/Gen6, 112G/224G Ethernet, PDN design
This role has been open 177 days — well above the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
72 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1435 · 106 employers |
| Median days open | 177 d | 72 d (+105 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: SI simulations, high-speed serial interfaces, PCIe Gen5/Gen6, 112G/224G Ethernet, PDN design
Who's hiring in this category
- Synopsys · 35 open roles · median 37 d
- AMD · 27 open roles · median 43 d
- Qualcomm · 21 open roles · median 67 d
- Cadence Design Systems · 20 open roles · median 149 d
- Micron Technology · 14 open roles · median 40 d
- Apple · 9 open roles · median 26 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.
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