Analog Layout Engineer (eInfochips) - US-TX-Texas (Remote Employees), United States
Originally posted 24 October 2026 by the employer.
Physical silicon layout for SerDes, ADCs, DACs, and PLLs on TSMC N3 and N5 FinFET nodes.
About the role
The High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency and high-speed mixed-signal circuits, including SerDes, ADCs, DACs, and PLLs. The role focuses on advanced FinFET nodes, specifically TSMC N3 and N5.
What you'll do
- Create block-level and chip-top-level floor plans, manage hierarchical block integration, and perform micro-bump or package-aware co-design. - Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding techniques including coaxial, differential, and ground shields. - Ensure complete physical verification closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection. - Travel to client office locations as requested by leadership.
What you'll need
- 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes. - Direct layout experience at lower nodes, specifically TSMC N3 or N5. - Demonstrated experience closing DRC, LVS, ERC, antenna rules, and EM/IR reliability checks. - Experience with physical layout of high-speed mixed-signal blocks such as SerDes, ADCs, DACs, or PLLs. - Bachelor's degree in electrical engineering or a related technical field.
Skills: Analog Layout, DRC, LVS, FinFET, Virtuoso
This role has been open 0 days — well below the 32-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
72
|
Median days open
32 d
|
Median salary
$164k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | eInfochips | All employers we track in this specialty (72 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 72 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1435 · 106 employers |
| Median days open | 0 d | 32 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $164k |
Skills observed across this category: Analog Layout, DRC, LVS, FinFET, Virtuoso
Who's hiring in this category
- Analog Devices · 9 open roles · median 32 d
- Celero · 8 open roles · median 56 d
- Renesas Electronics · 7 open roles · median 21 d
- Marvell Technology · 6 open roles · median 28 d
- Infineon Technologies · 5 open roles · median 9 d
- NXP Semiconductors · 5 open roles · median 18 d
How we counted: 72 open Analog IC Design (Analog Layout) roles from 23 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.