SI/PI Engineer - San Jose, United States
Originally posted 30 April 2026 by the employer — open 132 days.
About the role
This role involves owning the Signal Integrity and Power Integrity (SI/PI) methodology for high-speed PCB and system designs, from architecture through final release, to ensure electrical margins are met across multi-gigabit data rate interfaces.
What you'll do
- Perform pre- and post-layout SI simulations for high-speed serial interfaces, including PCIe Gen5/Gen6 and 112G/224G Ethernet.
- Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines.
- Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements.
- Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation.
- Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave.
- Support bring-up, debug signal quality issues, and document root-cause findings with clear corrective actions.
What you'll need
- B.S. or M.S. in Electrical Engineering or a closely related discipline.
- 5+ years of hands-on SI/PI experience on high-speed designs (>1 Gbps serial links or DDR4/5 and HBM3/4 memory interfaces).
- Proficiency with industry SI/PI EDA tools (Cadence Sigrity, Ansys SIwave/HFSS, Keysight ADS, or equivalent).
- Strong understanding of transmission line theory, return-loss, insertion-loss, crosstalk, eye-diagram analysis, and jitter decomposition.
- Experience with PDN modelling, target impedance methodology, and DC IR analysis.
- Working knowledge of multi-layer PCB stack-up design and controlled-impedance trace routing.
- Hands-on lab skills: S-parameter measurements with VNA, time-domain reflectometry (TDR), BERT operation, and oscilloscope probing techniques.
Nice to have
- Prior work in data center, AI/ML accelerator, networking, or high-performance computing (HPC) hardware environments.
- Experience scripting automated SI/PI simulation flows using Python or MATLAB.
Skills: SI simulations, high-speed serial interfaces, PCIe Gen5/Gen6, 112G/224G Ethernet, PDN design
This role has been open 132 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1317 · 100 employers |
| Median days open | 155 d | 91 d (+64 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI simulations, high-speed serial interfaces, PCIe Gen5/Gen6, 112G/224G Ethernet, PDN design
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.