SerDes IP Systems Engineering Director - San Jose, United States
$178,500 - $331,500 USD yearly
Originally posted 22 June 2026 by the employer — open 80 days.
Contribute to the development of advanced D2D SerDes IP products.
About the role
This role involves leading the D2D Systems analysis team and contributing to the development of advanced D2D SerDes IP products. This is a key contributor and driver for the R&D team that defines, models, and analyzes high performance D2D SerDes IP microarchitecture, link budget, and specifications.
What you'll do
- Lead the D2D Systems analysis team and contribute to technical development.
- Define, model, and analyze high performance D2D SerDes IP microarchitecture, link budget, and specifications.
- Develop infrastructure for robust product development, systems modeling analysis, and testing.
- Develop statistical and linear systems analysis of the link, model nonidealities, and determine design specifications for circuit designers.
- Provide guidelines regarding signal integrity and power integrity to customers.
- Guide the package design team based on in-package D2D link channel analysis.
What you'll need
- PhD or M.S. in Electrical/Computer Engineering (or similar degree).
- 10+ years of experience working with high speed high performance SerDes and PHYs.
- Strong mathematical skills, particularly relating to linear systems (Fourier analysis, filter theory, etc.).
- Deep understanding of high speed SerDes architecture.
- Deep knowledge of communication systems fundamentals and wireline communications.
- Strong coding skills for simulation and modelling, as well as data analysis.
- Experience generating systems or IBIS-AMI models.
- Experience using system simulation tools, especially Matlab, Perl, and other scripting tools.
- Good knowledge of signal processing (DSP) algorithms and architecture.
- Good working knowledge of physics of signal propagation.
Nice to have
- D2D link experience.
- Familiarity with emerging D2D standards such as UCIe.
- Familiarity with advanced technology nodes (7nm and below).
- Experience with 3D electromagnetic simulation tools.
Skills: SerDes IP, D2D SerDes, signal integrity, power integrity, system modeling, wireline communications
This role has been open 169 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes IP, D2D SerDes, signal integrity, power integrity, system modeling, wireline communications
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.