Senior VLSI Design Engineer (IO Design, High Speed DDR) - Bengaluru, India
SanDisk
Bengaluru, India
Full-time
3 months ago
Analog & Mixed-Signal Design
Originally posted 15 July 2026 by the employer — open 57 days. Relisted by the employer on 7 August 2026.
About the role
What you'll do
- Design high Speed IO Blocks.
- Conduct Powerbus analysis and Jitter / High speed timing closure.
- Work with cross-functional teams like Layout and verification.
- Propose innovative design solutions and methodologies for future generation.
What you'll need
- Bachelor's or Master's degree in Electronics & Telecommunication/Electrical engineering (VLSI Design).
- 4+ years of experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6.
- Familiarity with custom design methodology & flow, Calibration, JTAG design requirements.
- Understanding of High-speed IO circuit design including DLL, Rx, Tx, and clocking circuits.
- Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding, and parasitic optimization.
- Familiarity with spice tools like finesim, hspice.
Nice to have
- NAND Flash Design knowledge.
- Familiarity with package/board/Power integrity /signal integrity constraints.
- Automation & scripting knowledge.
Skills: high-speed IO, DDR, DLL, Rx, Tx, clocking circuits
Market context
This role has been open 56 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 5 | 217 |
| Median days open | 29 d | 91 d (−62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed IO, DDR, DLL, Rx, Tx, clocking circuits
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.