Senior Technical Staff-Design (Signal and Power Integrity) - CA - San Jose - 3850 N. First St, United States
$91,000 - $232,000 USD yearly
Originally posted 16 April 2026 by the employer.
About the role
Responsible for developing and driving Signal and Power Integrity methodologies for high-speed FPGA products in San Jose, CA. You will work with SIPI engineers and a global cross-functional team to deliver system-level solutions across die, package, and board designs.
What you'll do
- Conduct pre-layout and post-layout SIPI simulations to optimize signal integrity and power integrity performance at the system level. - Build system-level topologies for co-simulations covering Power Delivery Network (PDN) design, noise mitigation, and high-speed SerDes transceivers. - Perform high-speed SIPI analysis across die, package, and boards, interpreting channel loss mechanisms, optimizing eye diagrams, and executing jitter analysis and crosstalk reduction. - Influence die design changes based on simulation results and implement SI/PI strategies throughout the product development lifecycle. - Develop methodologies for robust PDN systems and SerDes transceiver performance, including equalization techniques and advanced jitter analysis. - Provide technical guidance and mentorship to other SIPI engineers within the team.
What you'll need
- Bachelor of Science (BS) degree in Electrical Engineering or Electronic Engineering with 15+ years of relevant experience, including 10+ years of direct, hands-on experience in Signal Integrity and Power Integrity (SIPI). - Extensive practical experience in Printed Circuit Board (PCB) design, layout principles, and PCB manufacturing processes. - In-depth understanding of S-Parameter extraction techniques, system-level channel modeling, via modeling, connector Time Domain Reflectometry (TDR) analysis, and stack-up analysis. - Expertise in equalization techniques, jitter analysis, eye diagram analysis, and channel impairments (return loss, insertion loss). - Hands-on experience with field solvers and simulation tools: Ansys HFSS, Ansys SIwave, Mentor Graphics HyperLynx, HSPICE, RedHawk, and Keysight ADS. - Hands-on lab experience with Vector Network Analyzers (VNAs), Time Domain Reflectometers (TDRs), Sampling and Real-Time Oscilloscopes, Bit Error Rate Testers (BERTs), and de-embedding techniques.
Nice to have
- Master of Science (MS) degree in a relevant engineering field. - Experience with IBIS-AMI modeling, validation, and correlation. - High-Speed SerDes experience troubleshooting channel-related issues for 32G transceivers and beyond. - Experience in package analysis and optimization covering thermal and mechanical considerations.
Skills: Signal Integrity, Power Integrity, SerDes, Jitter analysis, PDN design
This role has been open 125 days — well above the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
72 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 33 | 1439 · 106 employers |
| Median days open | 125 d | 72 d (+53 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: Signal Integrity, Power Integrity, SerDes, Jitter analysis, PDN design
Who's hiring in this category
- Synopsys · 35 open roles · median 37 d
- AMD · 27 open roles · median 43 d
- Qualcomm · 21 open roles · median 67 d
- Cadence Design Systems · 20 open roles · median 149 d
- Micron Technology · 14 open roles · median 40 d
- Apple · 9 open roles · median 26 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.
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