Senior Technical Staff-Design (Signal and Power Integrity) - CA - San Jose - 3850 N. First St, United States
$91,000 - $232,000 USD yearly
Originally posted 16 April 2026 by the employer — open 147 days.
Develop Signal and Power Integrity methodologies for high-speed FPGA products.
About the role
This role involves developing and driving Signal and Power Integrity methodologies for high-speed FPGA products. You will work with a global cross-functional team to provide system-level solutions.
What you'll do
- Develop and drive Signal and Power Integrity methodologies for high-speed FPGA products.
- Conduct extensive Signal Integrity and Power Integrity (SIPI) simulations (pre-layout and post-layout) across Die, Package, and Boards.
- Influence die changes based on simulation results to ensure optimal SIPI performance.
- Develop and refine methodologies for running simulations to ensure robust Power Delivery Network (PDN) systems.
- Develop strategies and methodologies to guarantee robust performance of high-speed SerDes transceivers, including equalization techniques and advanced jitter analysis.
- Provide technical guidance and mentorship to other SIPI engineers.
What you'll need
- Bachelor of Science (BS) degree in Electrical Engineering or Electronic Engineering.
- 15 years of relevant experience.
- 10 years of practical, hands-on experience directly related to Signal Integrity and Power Integrity (SIPI).
- Extensive practical experience in Printed Circuit Board (PCB) design and layout principles.
- Robust understanding of system-level SIPI design methodologies and analysis techniques (die-level, package-level, board-level).
- In-depth understanding of S-Parameter extraction techniques and system-level channel modeling.
- Expertise in via modeling, connector Time Domain Reflectometry (TDR) analysis, and stack-up analysis.
- Adept at equalization techniques, jitter analysis, eye diagram analysis, and addressing channel impairments (return loss, insertion loss).
- Strong, hands-on experience with industry-standard Field Solvers: Ansys HFSS, Ansys Siwave, Mentor Graphics Hyperlynx, and HSPICE, Redhawk.
- Experience with simulation tools: Keysight ADS and Mentor Graphics Hyperlynx for pre- and post-layout simulation and analysis.
- Hands-on experience with Vector Network Analyzers (VNAs), Time Domain Reflectometers (TDRs), Sampling and Real-Time Oscilloscopes, Bit Error Rate Testers (BERTs), de-embedding techniques, and jitter analysis equipment.
Nice to have
- High-Speed SerDes (Serializer/Deserializer) experience, especially troubleshooting channel-related issues for 32G transceivers and beyond.
- Experience in performing package analysis and optimization (thermal and mechanical considerations).
- Experience with IBIS-AMI modeling, validation, and correlation.
- Master of Science (MS) degree in a relevant engineering field.
Skills: Signal Integrity, Power Integrity, SerDes, Jitter analysis, PDN design
This role has been open 79 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 2 | 217 |
| Median days open | 124 d | 91 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signal Integrity, Power Integrity, SerDes, Jitter analysis, PDN design
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.