Senior System Power Architect

FPGA hardware and software

Originally posted 30 October 2026 by the employer.

About the role

The Senior System Power Architect drives power analysis and low-power optimization across Lattice FPGA hardware and software.

What you'll do

• Define low-power feature specifications, user flows, and algorithms, aligning software, marketing, and applications teams.
• Drive power-performance analysis to influence hardware and software roadmaps.
• Develop chip-level power estimation models covering dynamic, static, clock, memory, and I/O, correlating models with simulations and silicon.
• Establish power-aware RTL methodology and competitive benchmarks.
• Lead and mentor junior engineers across distributed teams.

What you'll need

• BS, MS, or PhD in EE, CE, CS, or a related field with 8+, 6+, or 3+ years of relevant experience.
• Knowledge of low-power design techniques.
• Deep expertise in RTL and gate-level power analysis and optimization, as well as power-aware synthesis and P&R.
• Hands-on experience with industry power and timing tools such as PrimePower, PrimeTime, SpyGlass, Joules, Voltus, or PowerArtist.
• Knowledge of STA and power/timing ECO flows.
• Proficiency in C/C++ and Python.

Nice to have

• Knowledge of FPGA architecture, design flows, and use cases.

Skills: low-power design, power modeling, PrimePower, RTL power analysis, FPGA architecture

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