Senior Staff Test Engineer - San Jose, United States
Originally posted 27 October 2026 by the employer.
Define ATE test strategy and hardware/software architectures for high-performance AI power solutions.
About the role
This role involves defining long-term ATE roadmaps, architecting scalable hardware and software testing platforms, and leading cross-functional collaborations across Product, Quality, Design, and Validation engineering. You will drive test strategy from initial product definition through global production release for high-performance AI power solutions.
What you'll do
- Design, implement, and govern standardized baseline software frameworks and hardware architectures across the global test organization. - Lead organizational quality planning, hardware/software architectural reviews, and establish design-for-test (DFT) guidelines for complex multi-die and power module products. - Direct product qualification, characterization, and cross-platform correlation strategies for power delivery technologies. - Partner with senior leadership in Product Engineering, Design, and Operations to manage production ramps, global manufacturing releases, yield optimization, and customer returns. - Oversee technical mentorship for engineering staff and manage technical alignment with third-party partners, foundries, and OSAT teams.
What you'll need
- Bachelor’s in Electrical Engineering, Computer Engineering, or a related field with 10+ years of semiconductor experience, or a Master's/Ph.D. with 8+ years. - 10+ years of experience architecting and developing automated test solutions on high-end ATE platforms such as Advantest V93K, COHU Diamondx, SPEA DOT800, or ETS364. - 8+ years of hands-on experience in ATE test development for complex analog, digital, high-power, and mixed-signal ICs. - Proficiency in programming languages such as C++ and Python for architecting production-grade reusable code templates, test APIs, and automation libraries. - Experience validating, debugging, and collecting characterization data using lab instruments such as oscilloscopes, spectrum analyzers, and source measure units. - Proficiency in high-performance ATE loadboard and probe card PCB layout design addressing parasitic reduction, signal integrity, and high-current power delivery.
This role has been open 0 days — well below the 39-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
562
|
Median days open
39 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (562 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 46 | 562 |
| Open roles in the wider Silicon Validation & Test family | 113 | 2249 · 112 employers |
| Median days open | 27 d | 39 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne · 75 open roles · median 31 d
- Infineon Technologies · 45 open roles · median 40 d
- Renesas Electronics (this employer) · 44 open roles · median 29 d
- Qualcomm · 31 open roles · median 39 d
- Micron Technology · 28 open roles · median 43 d
- Texas Instruments · 28 open roles · median 34 d
How we counted: 562 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.