Senior Staff Signal & Power Integrity Engineer - United States
$135,000 - $183,000 USD yearly
Originally posted 6 August 2024 by the employer — open 765 days.
This role focuses on PAM4 1.6T/3.2T DSPs and TIAs for data center connectivity.
About the role
The focus includes RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications.
What you'll do
- Perform signal integrity (SI) and power integrity (PI) simulations and optimization.
- Design and simulate high-speed signal interfaces and power distribution networks (PDN).
- Work on diverse products and applications including RF/mm-wave modems, 5G communication, and optical communications.
What you'll need
- Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory.
- Experience designing and simulating SI/PI solutions for high-speed system components (packages, PCB, connectors).
- Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI.
- Understanding of S-parameters, Smith Chart, and frequency domain analysis.
- Proficiency in 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers.
- Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE.
- Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network Analyzer (VNA), Oscilloscopes, TDR.
- Ability to manage package development in collaboration with cross-functional teams including systems, IC design, IC physical layout, package/PCB layout, and test/characterization.
Nice to have
- Experience with layout tools such as Cadence Allegro and APD.
- Understanding of IEEE and Optical standards to define design guidelines.
- Experience with electro-optic integration on packages; co-packaging of DC-DC convertors, regulator, TIAs, and optical drivers and multi-chip package design.
- Familiarity with IC design flows, floor-planning, IO ring design, on-chip decoupling, on-die EM/IR analysis.
- Understanding of TX/RX circuit designs and how system SI/PI impacts such circuits.
- Expertise in equalization techniques such as FIR, CTLE, DFE, FFE and different types of noise in the system and channels.
Skills: signal integrity, power integrity, SerDes, high-speed channel, S-parameters, HFSS
This role has been open 99 days — slightly above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MaxLinear | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 5 | 1317 · 100 employers |
| Median days open | 129 d | 91 d (+38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: signal integrity, power integrity, SerDes, high-speed channel, S-parameters, HFSS
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.