Senior Staff Physical Design Engineer - Noida, Uttar Pradesh, India
Originally posted 22 September 2026 by the employer — open 0 days.
About the role
This role involves complete ownership of PNR implementation for Qualcomm SoCs on latest nodes.
What you'll do
- Own PNR implementation including Floorplanning, Placement, Clock Tree Synthesis, and post-route on latest nodes.
- Apply expertise in Floorplanning, PNR, and STA flows.
- Optimize Placement and Clock Tree Synthesis.
- Understand signoff domains such as LEC, CLP, and PDN.
- Utilize knowledge of STA, Power analysis, FV, low power verification, and PV for signoff.
- Develop scripts using Perl/TCL in Unix/Linux environments.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- 12 years Hardware Engineering experience or related work experience.
- 12 years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
- Good hands-on experience on Floorplanning, PNR and STA flows.
- Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization.
- Good understanding on signoff domains– LEC/CLP/PDN knowledge.
- Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting.
Skills: PNR implementation, Floorplanning, Placement, Clock Tree Synthesis, STA, ASIC
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
606
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (606 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 115 | 606 |
| Open roles in the wider Physical Implementation family | 158 | 1407 · 108 employers |
| Median days open | 42 d | 61 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PNR implementation, Floorplanning, Placement, Clock Tree Synthesis, STA, ASIC
Who's hiring in this category
- Qualcomm (this employer) · 111 open roles · median 43 d
- Broadcom · 38 open roles · median 71 d
- NVIDIA · 38 open roles · median 46 d
- AMD · 35 open roles · median 41 d
- Synopsys · 27 open roles · median 60 d
- Renesas Electronics · 25 open roles · median 48 d
How we counted: 606 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.