Senior Staff Physical Design Engineer
Originally posted 22 September 2026 by the employer.
About the role
This role involves complete ownership of PNR implementation for Qualcomm SoCs on latest nodes.
What you'll do
- Own PNR implementation including Floorplanning, Placement, Clock Tree Synthesis, and post-route on latest nodes.
- Apply expertise in Floorplanning, PNR, and STA flows.
- Optimize Placement and Clock Tree Synthesis.
- Understand signoff domains such as LEC, CLP, and PDN.
- Utilize knowledge of STA, Power analysis, FV, low power verification, and PV for signoff.
- Develop scripts using Perl/TCL in Unix/Linux environments.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- 12 years Hardware Engineering experience or related work experience.
- 12 years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
- Good hands-on experience on Floorplanning, PNR and STA flows.
- Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization.
- Good understanding on signoff domains– LEC/CLP/PDN knowledge.
- Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting.
Skills: PNR implementation, Floorplanning, Placement, Clock Tree Synthesis, STA, ASIC
More semiconductor jobs: Qualcomm jobs · Physical design jobs · India jobs
This role has been open 44 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
708
|
Median days open
63 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (708 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 110 | 708 |
| Open roles in the wider Physical Implementation family | 154 | 1591 · 117 employers |
| Median days open | 57 d | 63 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PNR implementation, Floorplanning, Placement, Clock Tree Synthesis, STA, ASIC
Who's hiring in this category
- Qualcomm (this employer) · 109 open roles · median 57 d
- AMD · 61 open roles · median 37 d
- Broadcom · 49 open roles · median 37 d
- NVIDIA · 45 open roles · median 78 d
- Synopsys · 43 open roles · median 36 d
- Intel Corporation · 33 open roles · median 27 d
How we counted: 708 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.