Senior Digital PD Engineer
About the role
This role involves working on high-speed mixed-signal communication circuits and high-performance digital circuits that interface with analog circuitry as part of an overall system.
What you'll do
- Act as the global quality authority for the digital backend, owning sign-off for the complete RTL to GDSII flow.
- Orchestrate collaboration with EDA, Library, Memory, and IP teams to align execution priorities and improve implementation.
- Define and establish TI-wide physical design methodologies and flows, optimized for the latest process nodes.
- Drive the entire Physical Design lifecycle, including floorplanning, placement, CTS, routing, and full-chip implementation.
- Lead rigorous Static Timing Analysis (STA) and ensure total closure for EM, IR drop, and Physical Verification (DRC/LVS).
What you'll need
- 12+ years of hands-on experience in Physical Design / Digital Backend implementation.
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or VLSI Design.
- Proven expertise in RTL-to-GDSII flows using industry-standard EDA tools (Synopsys and/or Cadence toolchain).
- Demonstrated ability to own and deliver complex designs independently from specification through signoff.
- Deep knowledge of timing closure, power integrity, signal integrity, and physical verification (DRC/LVS/ERC).
- Strong understanding of process node design rules and implementation constraints.
Nice to have
- 12–18 years of progressive experience in physical design with increasing ownership and scope.
- Hands-on experience with mixed-signal designs — including analog-digital co-design, guard-ring strategies, substrate coupling mitigation, and mixed-signal floor planning.
- Prior experience in a Subject Matter Expert, methodology lead, or technical architect capacity.
- Familiarity with in-house or customized EDA flow development and scripting (Tcl, Python, Perl).
- Knowledge of DFT integration within the physical design flow (scan insertion, BIST, boundary scan).
- Exposure to power management architectures and low-power implementation techniques (multi-Vt, power gating, voltage islands).
Skills: RTL-to-GDSII, floorplanning, placement, CTS, routing, timing closure
More semiconductor jobs: Texas Instruments jobs · Physical design jobs · India jobs
This role has been open 43 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
708
|
Median days open
63 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (708 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 708 |
| Open roles in the wider Physical Implementation family | 15 | 1591 · 117 employers |
| Median days open | 107 d | 63 d (+44 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL-to-GDSII, floorplanning, placement, CTS, routing, timing closure
Who's hiring in this category
- Qualcomm · 109 open roles · median 57 d
- AMD · 61 open roles · median 37 d
- Broadcom · 49 open roles · median 37 d
- NVIDIA · 45 open roles · median 78 d
- Synopsys · 43 open roles · median 36 d
- Intel Corporation · 33 open roles · median 27 d
How we counted: 708 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.