Senior Staff Electrical Engineer
Lead verification architecture, methodology, and full-chip tapeout signoff for multiphase power-management ICs.
About the role
Renesas is seeking a Senior Staff Digital Design Verification Engineer to lead verification architecture, methodology, and signoff for digitally controlled power-management ICs. These devices integrate a multiphase digital control loop, telemetry, PMBus, AVSBus, an embedded microcontroller running production firmware, non-volatile configuration, and high-performance analog.
What you'll do
- Own chip-level verification strategy, test planning, and signoff for a power-management controller program from requirements through tapeout.
- Architect the UVM verification environment, including analog real-number modeling strategies, register models, and protocol agents for power-management buses.
- Define and enforce verification methodology across the team, establishing coverage models, assertion standards, checker requirements, and review practices.
- Lead technical reviews of verification plans, testbenches, and coverage models, and mentor engineers across the verification team.
- Drive the verification infrastructure roadmap across compute grid regression dispatch, coverage merge, and failure triage using Python, Perl, and Tcl.
- Debug complex failures across RTL, testbench, firmware, analog models, and specifications, feeding root causes back into methodology improvements.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 8 or more years of digital or mixed-signal design verification experience with a Bachelor's degree, or 6 or more years with a Master's degree.
- Experience serving as verification lead for at least one full-chip tapeout, owning the verification plan, coverage closure, and signoff recommendation.
- Proven experience architecting and building a UVM environment from the ground up, including agents, scoreboards, register models, sequence libraries, and functional coverage models.
- Expert knowledge of SystemVerilog and UVM, including constrained-random stimulus, functional coverage modeling, and SystemVerilog Assertions.
- Mixed-signal verification depth, including real-number or behavioral modeling for analog blocks and analog/digital co-simulation.
- Hardware/firmware co-verification experience on an embedded processor, including reading and writing embedded C and reasoning about register maps and non-volatile configuration.
- Proficiency in Linux, Python, and Perl or Tcl, along with experience managing regressions on a grid scheduler such as LSF.
Nice to have
- Verification of power-management ICs, voltage regulators, multiphase controllers, or digital control loops, including PWM generation, telemetry, fault handling, and power sequencing.
- Experience leading a migration from a directed or module-based testbench to UVM on an active program without disrupting ongoing regressions.
- Expertise with PMBus, AVSBus, high-speed power-management bus protocols, I2C, or SPI, including evaluating verification IP.
- Formal verification experience using JasperGold or equivalent for property checking, X-propagation, clock-domain crossing, or reset verification.
- Experience with Cadence Xcelium, SimVision, Verdi, vManager, JasperGold, and mixed-mode simulation with Spectre AMS.
- Experience with gate-level simulation, FPGA or emulation-based verification, silicon bring-up, and pre-silicon to silicon correlation.
Skills: UVM, SystemVerilog, testbench, power management, mixed-signal verification
More semiconductor jobs: Renesas Electronics jobs · Verification engineer jobs
First seen in our index 0 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1395
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1395 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 47 | 1395 |
| Open roles in the wider Digital Design & Verification family | 96 | 3614 · 122 employers |
| Median days since first seen | 22 d | 59 d (+37 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: UVM, SystemVerilog, testbench, power management, mixed-signal verification
Who's hiring in this category
- Qualcomm · 129 open roles · median 52 d
- NVIDIA · 109 open roles · median 73 d
- Apple · 107 open roles · median 16 d
- AMD · 82 open roles · median 63 d
- Synopsys · 80 open roles · median 57 d
- SiFive · 57 open roles · median 71 d
How we counted: 1395 open Design Verification (Design Verification) roles from 100 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.