About the role
This role is responsible for ensuring the quality of an SOC, IP, or subsystem in Beaverton, Oregon. You will review design and architecture specifications, understand functional and performance goals, and build verification environments to test effectively.
What you'll do
- Review design and architecture specifications in close collaboration with design and micro-architecture teams.
- Develop test plans, tests, and coverage plans, and help define verification methodology and test benches.
- Collaborate with design, architecture, and software teams to understand use cases and corner conditions to drive test cases.
- Run and triage regressions, track bugs, and analyze coverage to verify the design.
What you'll need
- Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.
- Experience utilizing SystemVerilog and UVM framework to write test bench code.
- Experience creating test plans using constrained random verification (CRV) or directed testing to verify ASICs.
- Experience utilizing C to write microprocessor tests for ASIC/Embedded tests.
- Experience implementing IP block test environments and test cases for ASICs, developing test coverage plans, collecting coverage, and resolving coverage gaps.
- Experience utilizing Xcelium, Questa, or VCS to analyze simulation failures, along with Python or Perl scripting to automate test bench analysis.
Skills: SystemVerilog, UVM, constrained random verification, ASIC, coverage
More semiconductor jobs: Apple jobs · Verification engineer jobs
First seen in our index 8 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 107 | 1412 |
| Open roles in the wider Digital Design & Verification family | 180 | 3617 · 122 employers |
| Median days since first seen | 17 d | 59 d (+42 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, constrained random verification, ASIC, coverage
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple (this employer) · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.