Senior/ Staff Design Automation Engineer, Scribe Layout Design Non-Array - Hyderabad - Phoenix Aquila, India
Originally posted 23 September 2026 by the employer.
About the role
This role involves the design, layout, and verification of CMOS electrical test structures for CMOS device development, Compact modeling, Reliability modeling, and Fab process monitoring within the Scribe Design Non-Array (SDNA) team.
What you'll do
- Identify problem areas, propose, and develop innovative solutions.
- Evaluate and implement new tools and technologies to improve current automation flows.
- Provide guidance and mentorship to junior team members.
What you'll need
- Advanced understanding of EDA tools and CAD flows.
- Proficiency in Generative AI, AI Agents, MCP (Model Context Protocol), and LLM-based automation.
- Experience developing and enabling programmatically defined P-cell (Parameterized layout generator) devices for CMOS modules.
- Ability to implement advanced methodologies for layout automation using SKILL/SKILL++.
- Deep knowledge of Python for data processing and tool enhancements.
- Good understanding of programming fundamentals and exposure to Skill/Skill++, Perl, Python, Tcl.
- Good understanding of basic CMOS process manufacturing, layout design rules, and layout design.
- Working knowledge of Linux.
- 5+ years of relevant experience.
- Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering or Electronics Engineering.
Skills: EDA tools, CAD flows, layout automation, SKILL/SKILL++, P-cell, DRC
This role has been open 0 days — well below the 85-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
682
|
Median days open
85 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (682 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 37 | 682 |
| Open roles in the wider Physical Implementation family | 71 | 1414 · 108 employers |
| Median days open | 118 d | 85 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: EDA tools, CAD flows, layout automation, SKILL/SKILL++, P-cell, DRC
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 148 d
- Synopsys · 55 open roles · median 62 d
- NVIDIA · 46 open roles · median 67 d
- Micron Technology (this employer) · 37 open roles · median 118 d
- Qualcomm · 37 open roles · median 64 d
- Intel Corporation · 28 open roles · median 28 d
How we counted: 682 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.