Senior STA Engineer - Noida, Uttar Pradesh, India
Originally posted 22 September 2026 by the employer — open 0 days.
About the role
This role involves static timing analysis and physical implementation aspects for high performance, high quality, low power products.
What you'll do
- Define, model, design, optimize, verify, validate, implement, and document IP development.
- Solve extreme critical timing bottleneck paths.
- Prepare complex ECOs for timing convergence through Tweaker / Tempus / Physical PT ECOs.
- Minimize power through implementation methods.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field.
- 3 years of experience in static timing analysis, constraints and other physical implementation aspects.
- Understanding of industry standard tools PT, Tempus, GENUS, Innovus, ICC.
- Experience with deep submicron process technology nodes.
- Knowledge of high performance and low power implementation methods.
- Expertise in Perl, TCL language.
Nice to have
- Solid grip on STA fixing aspects.
- Awareness of tricks for minimizing power.
- Willingness to push PPA to the best possible extent.
Skills: static timing analysis, timing convergence, PT, Tempus, physical implementation, deep submicron process
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
606
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (606 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 115 | 606 |
| Open roles in the wider Physical Implementation family | 158 | 1407 · 108 employers |
| Median days open | 42 d | 61 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: static timing analysis, timing convergence, PT, Tempus, physical implementation, deep submicron process
Who's hiring in this category
- Qualcomm (this employer) · 111 open roles · median 43 d
- Broadcom · 38 open roles · median 71 d
- NVIDIA · 38 open roles · median 46 d
- AMD · 35 open roles · median 41 d
- Synopsys · 27 open roles · median 60 d
- Renesas Electronics · 25 open roles · median 48 d
How we counted: 606 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.