Senior STA Engineer - Ahmedabad, Gujarat, India
Originally posted 11 September 2026 by the employer — open 0 days.
About the role
This role involves owning Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs.
What you'll do
- Own STA and timing signoff activities from synthesis through physical design and tape-out.
- Perform MCMM/MMMC timing analysis across all functional and test modes.
- Analyze and debug setup, hold, recovery, removal, min/max, and clock-related violations.
- Develop, review, and validate SDC constraints, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.
- Perform detailed clock tree and clock timing analysis, including skew, latency, uncertainty, jitter, and clock reconvergence.
- Drive timing closure in collaboration with RTL, synthesis, physical design, and ECO teams.
What you'll need
- Strong expertise in Static Timing Analysis and timing closure.
- Hands-on experience with Synopsys PrimeTime, Cadence Tempus, or equivalent STA tools.
- Excellent knowledge of SDC constraints and timing exceptions.
- Strong understanding of ASIC/SoC design, synthesis, physical design, and signoff flows.
- Expertise in MCMM/MMMC analysis.
- Good understanding of OCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing.
- Strong knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence.
- Proficiency in Tcl scripting.
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.
Skills: Static Timing Analysis, timing signoff, ASIC/SoC designs, SDC constraints, Synopsys PrimeTime
This role has been open 0 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
616
|
Median days open
57 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (616 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 616 |
| Open roles in the wider Physical Implementation family | 24 | 1419 · 106 employers |
| Median days open | 88 d | 57 d (+31 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Static Timing Analysis, timing signoff, ASIC/SoC designs, SDC constraints, Synopsys PrimeTime
Who's hiring in this category
- Qualcomm · 98 open roles · median 35 d
- NVIDIA · 42 open roles · median 50 d
- Broadcom · 41 open roles · median 60 d
- AMD · 31 open roles · median 46 d
- Synopsys · 28 open roles · median 63 d
- NXP Semiconductors · 23 open roles · median 80 d
How we counted: 616 open Physical Design (Physical Design) roles from 76 employers tracked in the SemiconductorJobs index, counted 11 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.