Senior STA Design Engineer - Bangalore-Technostar B1, India
Originally posted 24 September 2026 by the employer.
About the role
This role involves developing complex multi-mode/multi-corner timing constraints for RTL and signoff, and driving timing closure for sub-chip, subsystem, or full-chip designs.
What you'll do
- Develop complex multi-mode/multi-corner timing constraints compatible for RTL and signoff.
- Ensure constraints quality (SDC) using industry tools like Fishtail and GCA.
- Drive pre-route timing checks and QoR cleanup to eliminate SDC issues.
- Perform timing closure of one or multiple sub-chip/subsystem or full-chip designs.
- Ensure subsystem/full-chip level interface timing closure along with DRV closure.
- Generate timing ECO using DMSA/Tweaker tools.
What you'll need
- Experience in building timing constraints for IPs, blocks, and full-chip implementation in flat/hierarchical flows.
- Experience with analyzing timing reports and identifying design and constraints related issues.
- Proficiency with EDA tools including Synopsys Design Compiler/Primetime, Spyglass, Fishtail, and Tweaker.
- Experience in timing closure of high-frequency blocks and subsystems (>Ghz range).
- Good understanding of DFT modes requirements for timing signoff.
- Good understanding of SDC constraints, OCV, AOCV, and POCV analysis.
- Strong TCL/scripting knowledge.
- Bachelor's or Master's degree in Computer Engineering/Electrical Engineering.
Skills: timing constraints, SDC, timing closure, STA, Synopsys Primetime, TCL scripting
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
630
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (630 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 37 | 630 |
| Open roles in the wider Physical Implementation family | 62 | 1417 · 108 employers |
| Median days open | 34 d | 61 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: timing constraints, SDC, timing closure, STA, Synopsys Primetime, TCL scripting
Who's hiring in this category
- Qualcomm · 123 open roles · median 37 d
- NVIDIA · 39 open roles · median 48 d
- Broadcom · 38 open roles · median 73 d
- AMD (this employer) · 35 open roles · median 43 d
- Synopsys · 27 open roles · median 62 d
- Cadence Design Systems · 23 open roles · median 87 d
How we counted: 630 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.