Senior SoC Physical Layout & Full-Chip Integration Engineer - United States
$122,440 - $232,190 USD yearly
Originally posted 17 September 2026 by the employer — open 2 days.
Join the X-Chip Full-Chip Integration team.
About the role
This role involves developing methodologies, physical layouts, and silicon platforms for Intel Foundry, with a focus on custom layout methodologies, full-chip physical integration, and tapeout execution for advanced testchip and silicon lead vehicles.
What you'll do
- Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
- Develop and enhance custom layout methodologies and physical design flows.
- Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
- Analyze advanced-node design rules and contribute to design enablement for FinFET and Gate-All-Around (GAA) architectures.
- Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages.
- Coordinate cross-functional activities for tape-in readiness and database integrity.
What you'll need
- Master's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience, OR PhD with 1+ years of industry experience.
- Custom/analog/mixed-signal layout design experience in advanced technology nodes.
- Experience with Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
- Debugging skills in physical verification (LVS, DRC, and DFM) using Calibre or ICV.
- Proficiency in Tcl, Python, or SKILL for layout automation and full-chip database manipulation.
Nice to have
- Experience with top-level floorplanning, RDL/bump planning, or backside power delivery (PowerVia) implementation.
- Proven track record of collaborating with PDK and Technology Development teams on design rule definitions, test structure vehicles, or DRC suppression strategies.
- Experience managing physical tapeout schedules, IP tracking matrices, and formal physical design Quality Assurance (QA) flows.
- Familiarity with custom layout environments (such as Cadence Virtuoso) and translating custom databases into full-chip NDM flows.
- Previous related work experience in a semiconductor foundry.
Skills: full-chip integration, custom layout, DRC, LVS, DFM, tapeout
This role has been open 2 days — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
603
|
Median days open
58 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (603 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 603 |
| Open roles in the wider Physical Implementation family | 46 | 1371 · 106 employers |
| Median days open | 84 d | 58 d (+26 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: full-chip integration, custom layout, DRC, LVS, DFM, tapeout
Who's hiring in this category
- Qualcomm · 108 open roles · median 41 d
- Broadcom · 38 open roles · median 68 d
- NVIDIA · 38 open roles · median 49 d
- AMD · 35 open roles · median 38 d
- Synopsys · 27 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 45 d
How we counted: 603 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.