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NVIDIA

Senior Silicon Product Engineer, DFP – Manufacturing - CA, Santa Clara, United States

NVIDIA US, CA, Santa Clara, United States 1 month ago
Product Engineering & Quality

Originally posted 23 September 2026 by the employer.

About the role

The DFP Engineer – Manufacturing role defines and implements the validation and screening of new silicon features within high-volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale.

What you'll do

- Own end-to-end manufacturing test methodology across all test stages. - Translate system specs and product POR into DFP requirements, test content, coverage, and flows. - Define and maintain the DFP roadmap, including infrastructure and turning point planning. - Partner multi-functionally to implement test content, debug hooks, and coverage improvements. - Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs. - Define data and analytics frameworks to support yield analysis and continuous improvement.

What you'll need

- MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience). - 6+ years in silicon post-silicon validation and/or high-volume manufacturing test for complex SoCs, GPUs, CPUs, or similar. - Hands-on experience with test content bring-up, limit setting, correlation to characterization, and yield/coverage optimization. - Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis. - Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production. - Demonstrated ability to author structured technical documents and test plans used by global manufacturing and validation teams.

Skills: manufacturing test, DFP lifecycle, test content bring-up, limit setting, yield/coverage optimization, Python, MATLAB, R, SQL

Market context

This role has been open 200 days — well above the 80-day median for Product Engineering roles.

Product Engineering · Manufacturing Equipment

Open roles in category
158
Median days open
80 d
Median salary
$175k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How NVIDIA compares in Product Engineering hiring
Metric NVIDIA All employers we track in this specialty (158 roles · 48 employers)
Open roles in this specialty 7 158
Open roles in the wider Silicon Validation & Test family 85 2235 · 112 employers
Median days open 57 d 80 d (−23 d vs this employer)
Median salary (USD postings) — $175k

Skills observed across this category: manufacturing test, DFP lifecycle, test content bring-up, limit setting, yield/coverage optimization, Python

Who's hiring in this category

  • Texas Instruments · 12 open roles · median 58 d
  • Micron Technology · 11 open roles · median 183 d
  • AMD · 10 open roles · median 109 d
  • onsemi · 10 open roles · median 87 d
  • Analog Devices · 8 open roles · median 66 d
  • Entegris · 8 open roles · median 98 d

How we counted: 158 open Product Engineering (Manufacturing Equipment) roles from 48 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.

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US, CA, Santa Clara, United States
On-site
1 month ago

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