Originally posted 30 October 2026 by the employer.
About the role
As part of the Silicon CoDesign team, you will define product performance, power, and efficiency goals by connecting silicon capabilities with customer workloads and system-level solutions.
What you'll do
- Define product architecture performance, power, and efficiency goals, priorities, and tradeoffs based on customer workloads.
- Architect performance and power management features and system-level solutions from concept through silicon bring-up to shipping products.
- Benchmark competing architectures to prioritize investments improving performance, power efficiency, and product differentiation.
- Define operating points, configurations, and binning strategies with engineering teams while validating models against silicon data.
- Lead technical reviews and mentor engineers across the computing stack.
What you'll need
- MS or PhD in EE, CE, CS, systems engineering, or equivalent experience.
- 12+ years of experience in silicon or system performance and power, with ownership of product architecture or technical strategy.
- Deep silicon performance and power expertise, including device behavior, voltage-frequency characteristics, process variation, power management, and electrical and thermal limits.
- Broad CPU, GPU, or SoC architecture knowledge, including memory, interconnects, and hardware/software co-design.
- Experience with first-principles modeling, workload analysis, competitive benchmarking, statistics, and data analysis.
Skills: silicon architecture, power management, voltage-frequency, workload analysis, binning strategy
More semiconductor jobs: NVIDIA jobs · SoC design jobs · California jobs
This role has been open 0 days — well below the 72-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
469
|
Median days open
72 d
|
Category median salary (all employers)
$233k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (469 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 469 |
| Open roles in the wider Digital Design & Verification family | 257 | 3355 · 114 employers |
| Median days open | 73 d | 72 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $233k |
Skills observed across this category: silicon architecture, power management, voltage-frequency, workload analysis, binning strategy
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA (this employer) · 52 open roles · median 71 d
- Apple · 44 open roles · median 22 d
- AMD · 39 open roles · median 60 d
- Arm Holdings · 30 open roles · median 3 d
- Micron Technology · 21 open roles · median 107 d
How we counted: 469 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.