Senior Signal Integrity Engineer – LPU Packaging - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 24 July 2026 by the employer — open 48 days.
About the role
This role involves driving high-speed SerDes channel design, simulation, and correlation for advanced packages and data center platforms.
What you'll do
- Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces.
- Develop and execute simulation flows for 2.5D, 3D, and multi-die integration, focusing on channel loss, discontinuities, return path behavior, and crosstalk.
- Build and optimize chip-package-board co-simulation methodologies for HPC and data center systems.
- Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, and sockets.
- Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts.
- Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques.
What you'll need
- 8+ years of industry experience in signal integrity, high-speed interconnect design, or hardware development roles.
- Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior.
- Proven experience with high-speed SerDes design and analysis for advanced packaging or large-scale system applications.
- Hands-on experience with Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, or equivalent SI tools.
- Experience building and using channel models, S-parameters, IBIS-AMI based flows, and time/frequency-domain analysis techniques.
- Strong understanding of NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end-to-end channel budgets.
Skills: high-speed SerDes, signal integrity, advanced packages, PCIe, CXL, NVLink
This role has been open 80 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 10 | 217 |
| Median days open | 95 d | 91 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed SerDes, signal integrity, advanced packages, PCIe, CXL, NVLink
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA (this employer) · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.