Senior Signal Integrity Engineer - Austin, Texas, United States
Originally posted 15 June 2026 by the employer — open 87 days.
About the role
This role involves developing, validating, and optimizing high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. It focuses on hands-on measurement, simulation correlation, and cross-functional technical communication at the intersection of silicon, package, interconnect, board, and system design.
What you'll do
- Perform end-to-end signal integrity analysis for blade- and rack-level system architectures.
- Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, I2C.
- Conduct time-domain and frequency-domain simulations using Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, or SPICE.
- Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes.
- Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology.
- Prepare and communicate validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and stakeholders.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience in signal integrity for high-speed digital systems.
- Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes.
- Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and crosstalk.
- Knowledge of high-speed interfaces such as PCIe Gen4/5/6, Ethernet, DDR, SerDes.
- Experience with SI/PI simulation tools such as HFSS, ADS, Sigrity, CST, or SPICE.
- Ability to correlate lab measurements with simulations and use data to guide design decisions.
Nice to have
- Experience in hyperscale, data center, cloud infrastructure, or advanced compute hardware environments.
- Experience with blade, backplane, board-to-board, cable, or rack-level interconnect architectures.
- Knowledge of thermal and mechanical considerations that impact SI/PI performance.
- Experience with calibration, de-embedding, fixture design, lab automation, or measurement methodology development.
- Experience using Python or MATLAB for simulation automation, measurement automation, and data analysis.
Skills: Signal Integrity Engineer, high-speed signaling solutions, PCIe Gen4/5/6, Ethernet, DDR, SerDes, signal integrity analysis, hands-on measurement
This role has been open 85 days — below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Graphcore | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 3 | 217 |
| Median days open | 49 d | 91 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signal Integrity Engineer, high-speed signaling solutions, PCIe Gen4/5/6, Ethernet, DDR, SerDes, signal integrity analysis, hands-on measurement
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.