Senior Signal Integrity Engineer
$127,200 - $190,800 USD yearly
Originally posted 19 August 2026 by the employer.
About the role
This individual contributor role within the CHS Signal Integrity organization is responsible for end-to-end signal integrity and power integrity architecture, analysis, and signoff for mobile, compute, automotive, and other connectivity platforms. The role focuses on high-speed interfaces like PCIe Gen4/5/6/7, LPDDR4/5/6, USB4, UFS, 10G–112G PHYs, and MIPI CSI/DSI.
What you'll do
- Own end-to-end SI/PI closure for programs from pre-silicon to post-silicon to production.
- Define design targets and layout design guidelines for high-speed interfaces.
- Influence architecture decisions early in the product lifecycle and ensure SI/PI alignment with product KPIs.
- Ensure compliance to standards such as JEDEC, PCI-SIG, MIPI, and IEEE.
- Lead debug of eye collapse, jitter margin issues, crosstalk, power noise, and silicon-package-board interactions.
- Drive improvements in methods for system SI/PI and lead design reviews and signoff decisions.
What you'll need
- 4 years of experience in Signal Integrity, Power Integrity, or high-speed systems.
- Expertise in Transmission line theory, EM fundamentals, SI/PI interactions, and jitter/noise coupling.
- Hands-on experience with tools such as HFSS, ADS, Sigrity, CST, SIwave, and HSPICE.
- Hands-on experience with measurement instruments such as VNA, TDR, and real-time scopes.
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field with 2+ years of System/Package Design/Technology Engineering experience OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field with 1+ year of experience OR PhD in Chemical Engineering, Electrical Engineering, or Mechanical Engineering.
Skills: Signal Integrity, Power Integrity, high-speed interfaces, PCIe Gen4/5/6/7, LPDDR4/5/6, SI/PI closure
This role has been open 40 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 75 | 1385 · 107 employers |
| Median days open | 58 d | 76 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Signal Integrity, Power Integrity, high-speed interfaces, PCIe Gen4/5/6/7, LPDDR4/5/6, SI/PI closure
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm (this employer) · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.