Senior Serdes System Design Engineer/Architect - United States
$108,000 - $192,000 USD yearly
Originally posted 25 March 2026 by the employer — open 169 days. Relisted by the employer on 14 August 2026.
Design, verify, and implement advanced signal processing algorithms for high-speed Serdes at speeds of 100G+.
About the role
This role involves the design, verification, and implementation of advanced signal processing algorithms for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will focus on Serdes at speeds of 100G+.
What you'll do
- Develop channel models and run simulations to define Serdes architecture.
- Define and document signal processing block requirements, architecture, and lab test plans.
- Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
- Develop and run system-level simulation suites to evaluate architectural tradeoffs.
- Work with the design team to perform vector matching verification with RTL simulations.
- Develop, test, and debug firmware associated with physical layer functionality.
What you'll need
- Expert knowledge in Communication Theory.
- Expert knowledge in Digital Signal Processing algorithms.
- Working knowledge of Analog circuit behavior.
- Working knowledge of Transmission line theory and s-parameter.
- Expert in MATLAB, C/C++ programming.
- B.S.E.E. with 12+ years or M.S.E.E. with 10+ years relevant experience.
Nice to have
- Experience in designing high-speed Clock and Data Recovery (CDR) PLLs.
- Experience in equalization techniques for wireline communication applications such as read-channel.
- RTL coding.
- Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards.
Skills: SerDes, DSP, PAM modulation, adaptive equalizers, FEC, MATLAB, C/C++
This role has been open 164 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 11 | 217 |
| Median days open | 142 d | 91 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes, DSP, PAM modulation, adaptive equalizers, FEC, MATLAB
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom (this employer) · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.