Senior Principal SOC Power Lead - San Jose, California, United States

Originally posted 21 October 2026 by the employer.

About the role

As Senior Principal SOC Power Lead, you will drive power analysis, modeling, and optimization for System-on-Chip (SoC) solutions while leading a team of power engineers responsible for pre- and post-silicon power convergence. You will collaborate across architecture, design, verification, and product teams to achieve performance-per-watt targets.

What you'll do

- Lead pre- and post-silicon power convergence, collaborating with architecture, design, verification, and product teams. - Develop power modeling methods and deliver on-time product performance and power targets. - Define workflows to improve power analysis accuracy, turnaround time, and correlation to silicon. - Establish project plans, drive multiple technical projects, and mentor junior power engineers.

What you'll need

- Expertise in RTL and Netlist based power analysis and sign-off flows, EDA tools, and SoC physical design. - Knowledge of ASIC design power dependencies, including technology node, mixed Vt design, standard cell and memory library selection, voltage, and power domain partitioning. - Experience with simulation and emulation environments for creating workload scenarios (such as VCS, Questasim, Incisive, Veloce Strato, Palladium, or Zebu). - Experience leading projects, developing project plans, and mentoring junior engineers. - Presentation and technical communication skills to present technical content across teams.

Nice to have

- Understanding of software use-cases, benchmarks, and workloads interacting with hardware low-power features like clock and power gating, voltage/frequency scaling, and memory/logic retention. - Python for automation and modeling. - Experience with SoC use-case power budget decomposition to IP power budget.

Skills: SoC power analysis, RTL power, low power, power modeling, emulation