Senior Principal Physical Design Engineer - Bengaluru, Karnataka, India
Originally posted 30 September 2026 by the employer.
About the role
This role involves physical design engineering with a focus on complex SoC/silicon products.
What you'll do
- Drive full chip or block level designs from architecture to GDSII.
- Apply synthesis, timing closure, and formal verification at the block and full-chip level.
- Work with backend tools and methodologies for technologies 16nm or less.
- Collaborate with IP vendors for RTL and hard-mac blocks.
- Utilize DFT tools and techniques.
- Support or develop complex SoC/silicon products for Server, Storage, and/or Networking applications.
What you'll need
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- ≥6 years’ experience supporting or developing complex SoC/silicon products.
- Hands-on knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification, and other backend tools for 16nm or less technologies.
- Expertise in synthesis, timing closure, and formal verification (equivalence) at the block and full-chip level.
- Full chip or block level ownership from architecture to GDSII.
- Experience with Cadence and/or Synopsys physical design tools/flows.
- Familiarity with System Verilog/Verilog.
- Experience with DFT tools and techniques.
- Experience working with IP vendors for RTL and hard-mac blocks.
- Scripting skills in Python or Perl.
Nice to have
- Knowledge of design for test (DFT), stuck-at and transition scan test insertion.
- Familiarity with DFT test coverage and debug.
- Familiarity with ECO methodologies and tools.
Skills: synthesis, place and route, CTS, timing analysis/STA, Physical Verification, GDSII
This role has been open 1 day — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
636
|
Median days open
58 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (636 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 636 |
| Open roles in the wider Physical Implementation family | 24 | 1427 · 109 employers |
| Median days open | 106 d | 58 d (+48 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: synthesis, place and route, CTS, timing analysis/STA, Physical Verification, GDSII
Who's hiring in this category
- Qualcomm · 124 open roles · median 38 d
- AMD · 44 open roles · median 28 d
- Broadcom · 40 open roles · median 80 d
- NVIDIA · 38 open roles · median 55 d
- Synopsys · 26 open roles · median 48 d
- Micron Technology · 24 open roles · median 72 d
How we counted: 636 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 1 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.