Senior Principal Engineer, Physical Design - Austin, TX, United States
$179,900 - $266,180 USD yearly
Originally posted 28 August 2026 by the employer.
About the role
This role is responsible for the physical design and methodology for future high-performance processor chips.
What you'll do
- Lead RTL-to-GDSII implementation for SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS).
- Provide strategic leadership and technical direction to physical design teams for complex, high-performance SoCs.
- Drive the development and adoption of physical design methodologies, flows, and automation.
- Collaborate with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies.
- Manage project schedules, resources, and risk.
What you'll need
- Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of progressive experience in back-end physical design and verification, including significant leadership roles.
- Proven track record of leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts.
- Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges.
- In-depth understanding of current design technologies used in major foundries.
- Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure.
- In-depth knowledge of modern EDA tools and flows.
- Proficient in automation and scripting using Makefile, Tcl, Python, or Perl.
Nice to have
- Familiarity with AI/ML-driven optimization in physical design tools is a plus.
Skills: RTL-to-GDSII, synthesis, floorplanning, place and route, timing closure, physical design methodologies
This role has been open 30 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
624
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (624 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 624 |
| Open roles in the wider Physical Implementation family | 15 | 1399 · 108 employers |
| Median days open | 30 d | 63 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RTL-to-GDSII, synthesis, floorplanning, place and route, timing closure, physical design methodologies
Who's hiring in this category
- Qualcomm · 113 open roles · median 39 d
- AMD · 41 open roles · median 27 d
- NVIDIA · 38 open roles · median 52 d
- Broadcom · 37 open roles · median 77 d
- Synopsys · 27 open roles · median 66 d
- NXP Semiconductors · 26 open roles · median 76 d
How we counted: 624 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.