Senior Principal Engineer PD - Singapore
Originally posted 4 August 2026 by the employer — open 37 days.
This role focuses on high-performance transceiver IPs targeting TSMC 3nm.
About the role
This role is for a Senior Physical Design Engineer to join a high-performance design team. You will be working on transceiver IPs targeting the TSMC 3nm and advanced technology nodes.
What you'll do
- Perform block-level and top-level physical implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs.
- Collaborate with RTL and STA teams for handoffs and to support timing, area, and power convergence.
- Apply advanced physical design techniques for multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
- Work on EM/IR analysis and power grid optimization, congestion analysis and mitigation, clock skew optimization, and RC extraction-aware placement and routing.
- Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
- Ensure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools.
- Develop and maintain automation scripts in Tcl, Python, or Perl to improve physical design flows.
What you'll need
- 5+ years of experience in physical design, preferably with advanced technology nodes.
- Strong experience with floorplanning, placement, CTS, routing, and IR drop mitigation.
- Experience with signoff checks such as DRC, LVS, ANT, and ERC, along with debugging.
- Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.
- Experience working on high-frequency datapath and DSP-related designs.
- Solid scripting skills for automation and productivity enhancement.
- Hands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus.
Skills: floorplanning, placement, CTS, routing, DRC/LVS, TSMC 3nm
This role has been open 37 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
615
|
Median days open
57 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (615 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 615 |
| Open roles in the wider Physical Implementation family | 22 | 1427 · 104 employers |
| Median days open | 94 d | 57 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: floorplanning, placement, CTS, routing, DRC/LVS, TSMC 3nm
Who's hiring in this category
- Qualcomm · 99 open roles · median 34 d
- NVIDIA · 42 open roles · median 49 d
- Broadcom · 41 open roles · median 59 d
- AMD · 32 open roles · median 46 d
- Synopsys · 28 open roles · median 62 d
- Intel Corporation · 25 open roles · median 61 d
How we counted: 615 open Physical Design (Physical Design) roles from 74 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.