Senior Principal Engineer – Hardware Chip Lead, Connectivity BU - Santa Clara, CA, United States

Originally posted 30 July 2026 by the employer.

About the role

This role involves leading and managing hardware development for optical DSP programs within the Connectivity Business Unit, overseeing all hardware design phases from Plan of Record (POR) through Mass Production (MPR). The team develops chips in TSMC advanced process nodes for multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers.

What you'll do

• Serve as the primary hardware technical owner for an Optical DSP chip program.
• Finalize Product Requirements Documents and bring-up requirements.
• Provide technical leadership for full chip design and define high-level technical solutions.
• Lead end-to-end chip design execution across advanced CMOS nodes, including architecture, RTL, physical design, DFT, timing closure, and tape-out.
• Own the chip bring-up plan and execution, coordinating multi-site teams.
• Oversee silicon validation, PVT characterization, ATE test program development, qualification, and production release.

What you'll need

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of related professional experience.
• Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs, from architecture through tape-out and post-silicon productization.
• Deep expertise in high-speed mixed-signal SoC design, including SerDes (100G+/lane), DSP datapath, analog/digital integration, and advanced CMOS process nodes (5nm, 3nm).
• Strong understanding of the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out.
• Experience leading and coordinating cross-functional hardware teams across analog, digital, DV, DFT, PD, firmware, validation, and test engineering disciplines.
• Demonstrated ability to drive silicon bring-up, debug, and validation across multi-site global teams.

Nice to have

• Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimer products.
• Experience with eAVS or similar power optimization subsystems.
• Knowledge of SiPho integration and module-level validation.
• Experience working in a multi-site, globally distributed engineering organization.

Skills: chip lead, SoC/ASIC programs, high-speed mixed-signal, SerDes 100G+, tape-out, post-silicon productization