Senior Principal Design Verification Engineer - Chandler, United States
Originally posted 21 October 2026 by the employer.
Lead mixed-signal verification environments and AMS model integration for Automotive PMIC products.
About the role
This role leads verification efforts for the Automotive PMIC (Power Management Integrated Circuit) product line. The scope combines mixed-signal verification environment architecture with cross-functional leadership across multiple product platforms.
What you'll do
- Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs. - Develop and implement comprehensive verification plans for automotive PMIC products, ensuring compliance with automotive safety standards including ISO 26262 and AEC-Q200. - Set up and optimize Gate-Level Simulation (GLS) flows, correlating results with RTL simulation to resolve discrepancies across PVT corners. - Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces. - Collaborate with Design, Application Engineering, ATE, and Silicon Validation teams to troubleshoot analog-digital domain interactions and execute verification handoffs. - Mentor junior verification engineers and evaluate emerging verification technologies and AI-based solutions.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, or a related field. - 12+ years of experience in mixed-signal or analog circuit verification. - Hands-on experience with Real Number Model (RNM) and AMS model integration. - Proficiency in RTL and behavioral simulation tools such as Spectre and Xcelium. - Demonstrated experience with Verilog, SystemVerilog, and/or SPICE-based languages, alongside verification methodologies such as UVM, assertions, and coverage-driven verification. - Background verifying automotive PMIC or power management IC designs and debugging analog blocks like switched-mode regulators, LDOs, and bandgap circuits.
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 1233 |
| Open roles in the wider Digital Design & Verification family | 82 | 3298 · 115 employers |
| Median days open | 23 d | 64 d (−41 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.