Senior Principal Design Engineer - STA/Timing
$237,000 - $356,000 USD yearly
About the role
Ampere Computing is seeking a Senior Principal Design Engineer specializing in Static Timing Analysis (STA) and timing methodology to drive timing closure for CPU and SoC designs.
What you'll do
- Own and lead STA and timing closure activities across complex CPU, SoC, and IP designs.
- Define timing constraints, analysis methodologies, signoff criteria, and implementation guidelines.
- Drive timing closure from RTL through synthesis, place and route, signoff, and tapeout.
- Analyze and resolve setup, hold, recovery, removal, pulse-width, clock-domain, and variation-related timing issues.
- Develop and maintain timing constraints, including clocks, generated clocks, false paths, multicycle paths, asynchronous paths, and interface timing.
- Lead analysis across PVT corners, RC corners, operating modes, voltage domains, and variation models.
What you'll need
- Bachelor's degree with 12+ years of experience, Master's with 8+ years, or PhD with 5+ years in Electrical or Computer Engineering, semiconductor design, physical design, or timing analysis.
- Extensive hands-on experience with STA and timing closure for complex ASIC, CPU, SoC, or high-performance digital designs.
- Deep technical understanding of clock-tree design, OCV, AOCV, POCV, LVF, signal integrity, crosstalk, MCMM analysis, and ECO implementation.
- Hands-on experience with industry-standard tools such as Synopsys PrimeTime, PrimeClosure, Design Compiler, Fusion Compiler, ICC2, Cadence Tempus, or Innovus.
- Scripting and automation proficiency using Tcl, Python, Perl, or similar languages.
- Familiarity with Liberty, SDC, SPEF, parasitic extraction, UPF, and low-power design methodologies.
Skills: STA, timing closure, PrimeTime, SDC, timing constraints
More semiconductor jobs: Physical design jobs · Santa Clara jobs
This role has been open 13 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
717
|
Median days open
59 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ampere Computing | All employers we track in this specialty (717 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 717 |
| Open roles in the wider Physical Implementation family | 10 | 1606 · 116 employers |
| Median days open | 1 d | 59 d (−58 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: STA, timing closure, PrimeTime, SDC, timing constraints
Who's hiring in this category
- Qualcomm · 104 open roles · median 59 d
- AMD · 63 open roles · median 40 d
- Broadcom · 47 open roles · median 19 d
- NVIDIA · 45 open roles · median 81 d
- Synopsys · 44 open roles · median 38 d
- Intel Corporation · 32 open roles · median 30 d
How we counted: 717 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.