Implement and close mixed-signal ASIC partitions for high-speed parallel optical links using microLED transmitter arrays.
About the role
Avicena is seeking a physical design engineer to implement and close digital blocks and top-level partitions of a mixed-signal ASIC from netlist to clean signoff. The design supports high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers.
What you'll do
- Run synthesis, floorplanning, placement, clock tree synthesis, and routing for blocks and partitions.
- Close timing across modes and corners, and implement ECOs.
- Run signoff checks, including STA, IR drop and EM, physical verification, and logical equivalence.
- Integrate analog macros and repeated arrays following the macro handoff checklist.
- Maintain and improve implementation scripts.
- Support tapeout and post-tapeout ECOs.
What you'll need
- BS or MS in Electrical or Computer Engineering with 3+ years of ASIC physical design experience.
- Hands-on experience with Cadence Innovus or Synopsys ICC2/Fusion Compiler, and STA with Tempus or PrimeTime.
- Physical verification experience with Calibre or Pegasus.
- FinFET implementation experience.
- Scripting proficiency in Tcl and Python.
Nice to have
- Mixed-signal top-level integration.
- IR/EM analysis and fixing.
- DFT-aware implementation, such as scan chain reordering.
- Hierarchical implementation.
Skills: physical design, PnR, Innovus, ICC2, STA, FinFET
More semiconductor jobs: Physical design jobs · Sunnyvale jobs
This role has been open 4 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
717
|
Median days open
59 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Avicena | All employers we track in this specialty (717 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 717 |
| Open roles in the wider Physical Implementation family | 4 | 1606 · 116 employers |
| Median days open | 4 d | 59 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: physical design, PnR, Innovus, ICC2, STA, FinFET
Who's hiring in this category
- Qualcomm · 104 open roles · median 59 d
- AMD · 63 open roles · median 40 d
- Broadcom · 47 open roles · median 19 d
- NVIDIA · 45 open roles · median 81 d
- Synopsys · 44 open roles · median 38 d
- Intel Corporation · 32 open roles · median 30 d
How we counted: 717 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.