Lead digital implementation and signoff for mixed-signal ASICs integrated with microLED transmitter arrays and photodetector receivers.
About the role
The Physical Design Lead owns digital implementation of mixed-signal ASICs from synthesis through signoff, integrating the digital core with custom analog macros and dense repeated lane arrays. The position supports optical links built from arrays of microLED transmitters and photodetector receivers.
What you'll do
- Own the digital implementation flow from synthesis through signoff, including floorplan, power planning, placement, clock tree synthesis, routing, and ECOs.
- Define and maintain timing constraints with the digital team, and drive multi-mode, multi-corner (MMMC) timing closure including on-chip variation (OCV/AOCV/POCV).
- Plan the top-level floorplan and integrate custom analog macros and repeated arrays through agreed abstracts, timing models, pin interfaces, and power interfaces.
- Run early feasibility studies for congestion, timing, and power with preliminary netlists and macro abstracts prior to RTL freeze.
- Own implementation signoff covering STA, IR drop, EM, crosstalk, signal integrity, physical verification, and logical equivalence.
- Build scripted, reproducible flows, mentor and direct a PnR engineer, and coordinate with CAD, foundries, and package/SI-PI teams.
What you'll need
- BS in Electrical or Computer Engineering (or related discipline) with 10+ years of ASIC physical design experience, including full-chip or block netlist-to-GDS ownership for multiple tapeouts.
- Hands-on expertise with Cadence Innovus/Genus or Synopsys Fusion Compiler/ICC2, along with signoff tools including Tempus or PrimeTime, Voltus or RedHawk, Quantus or StarRC, and Calibre or Pegasus.
- Strong command of timing constraints, MMMC, OCV/AOCV/POCV, clock tree strategies, and ECO flows.
- FinFET implementation experience, including multi-patterning and advanced-node design rules.
- Experience integrating hard analog/mixed-signal macros into a digital top level.
- Strong Tcl and Python scripting skills.
Nice to have
- Implementation experience with mixed-signal chips featuring high-speed I/O, SerDes, or arrays of repeated lanes.
- Experience with hierarchical implementation and top-level assembly of large chips.
- Low-power implementation experience with multiple voltage domains using UPF.
- Experience leading engineers and managing contractors.
- Direct work with foundries and packaging teams through tapeout.
Skills: physical design, PnR, Innovus, Fusion Compiler, STA, timing closure
More semiconductor jobs: Physical design jobs · Sunnyvale jobs
This role has been open 4 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
717
|
Median days open
59 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Avicena | All employers we track in this specialty (717 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 717 |
| Open roles in the wider Physical Implementation family | 4 | 1606 · 116 employers |
| Median days open | 4 d | 59 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: physical design, PnR, Innovus, Fusion Compiler, STA, timing closure
Who's hiring in this category
- Qualcomm · 104 open roles · median 59 d
- AMD · 63 open roles · median 40 d
- Broadcom · 47 open roles · median 19 d
- NVIDIA · 45 open roles · median 81 d
- Synopsys · 44 open roles · median 38 d
- Intel Corporation · 32 open roles · median 30 d
How we counted: 717 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.